Reference voltage circuit and semiconductor device
View Patent ↗A reference voltage circuit includes: a depletion type MOS transistor and an enhancement type MOS transistor connected in series, and having gates thereof connected in common, the enhancement type MOS transistor providing a reference voltage from a drain thereof, the depletion type MOS transistor including at least a first depletion type MOS transistor and a second depletion type MOS transistor connected in series; and a capacitor having one end connected to a drain of the first depletion type MOS transistor, and the other end connected to a source of the first depletion type MOS transistor.
1. A reference voltage circuit comprising:
a depletion type MOS transistor and an enhancement type MOS transistor connected in series, and having gates thereof connected in common, the enhancement type MOS transistor providing a reference voltage from a drain thereof, the depletion type MOS transistor comprising at least a first depletion type MOS transistor and a second depletion type MOS transistor connected in series; and
a capacitor having one end connected to a drain of the first depletion type MOS transistor, and the other end connected to a source of the first depletion type MOS transistor.
2. The reference voltage circuit according to claim 1 , wherein the second depletion type MOS transistor has a higher current supply capability than the first depletion type MOS transistor.
3. The reference voltage circuit according to claim 1 , further comprising a current mirror circuit which mirrors a current flowing through the depletion type MOS transistor to a current flowing to the drain of the enhancement type MOS transistor.
4. The reference voltage circuit according to claim 1 , wherein the second depletion type MOS transistor has a higher breakdown voltage between the gate and the drain and a higher breakdown voltage between the source and the drain than the first depletion type MOS transistor.
5. The reference voltage circuit according to claim 1 , further comprising a third depletion type MOS transistor having a gate connected to the source of the second depletion type MOS transistor and cascode-connected to the second depletion type MOS transistor.
6. The reference voltage circuit according to claim 2 , further comprising a current mirror circuit which mirrors a current flowing through the depletion type MOS transistor to a current flowing to the drain of the enhancement type MOS transistor.
7. The reference voltage circuit according to claim 2 , wherein the second depletion type MOS transistor has a higher breakdown voltage between the gate and the drain and a higher breakdown voltage between the source and the drain than the first depletion type MOS transistor.
8. The reference voltage circuit according to claim 2 , further comprising a third depletion type MOS transistor having a gate connected to the source of the second depletion type MOS transistor and cascode-connected to the second depletion type MOS transistor.
9. The reference voltage circuit according to claim 5 , wherein the third depletion type MOS transistor has a higher breakdown voltage between the gate and the drain and a higher breakdown voltage between the source and the drain than the second depletion type MOS transistor.
10. A reference voltage circuit comprising:
a depletion type MOS transistor and an enhancement type MOS transistor connected in series and having gates thereof connected in common, the enhancement type MOS transistor providing a reference voltage from a drain thereof, the depletion type MOS transistor comprising at least a first depletion type MOS transistor and a second depletion type MOS transistors connected in series;
a third depletion type MOS transistor having a gate connected to a source of the second depletion type MOS transistor and cascode-connected to the second depletion type MOS transistor; and
a capacitor having one end connected to a source of the third depletion type MOS transistor, and the other end connected to a source of the first depletion type MOS transistor.
11. The reference voltage circuit according to claim 10 , wherein the third depletion type MOS transistor has a higher current supply capability than the first and second depletion type MOS transistors.
12. The reference voltage circuit according to claim 10 , further comprising a current mirror circuit which mirrors a current flowing through the depletion type MOS transistor to a current flowing to the drain of the enhancement type MOS transistor.
13. The reference voltage circuit according to claim 10 , wherein the third depletion type MOS transistor has a higher breakdown voltage between the gate and the drain and a higher breakdown voltage between the source and the drain than the second depletion type MOS transistor.
14. The reference voltage circuit according to claim 11 , further comprising a current mirror circuit which mirrors a current flowing through the depletion type MOS transistor to a current flowing to the drain of the enhancement type MOS transistor.
15. The reference voltage circuit according to claim 11 , wherein the third depletion type MOS transistor has a higher breakdown voltage between the gate and the drain and a higher breakdown voltage between the source and the drain than the second depletion type MOS transistor.
16. A semiconductor device comprising the reference voltage circuit according to claim 1 .
17. A semiconductor device comprising the reference voltage circuit according to claim 10 .