IP Library Granted Patent US 10,810,082
Granted Patent B2
US 10,810,082 · App. 16/227,869 · Granted Oct 20, 2020

Networked storage redundancy scheme

Inventors: Yaniv Romem (Jerusalem, IL); Ofer Oshri (Kfar Saba, IL); Omri Mann (Jerusalem, IL); Kirill Shoikhet (Tel Aviv, IL); Daniel Herman Shmulyan (Beer Yaaqov, IL); James Jackson (Colorado Springs, CO)
Assignee: Excelero Storage Ltd.
G06F11/1076G06F11/1004G06F12/10G06F2212/1044
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Quick Facts
Patent No.
US 10,810,082
App. No.
16/227,869
Granted
Oct 20, 2020
Kind
B2
Abstract

A system and method for improved redundancy in storage devices are disclosed. The method includes receiving a first data block for writing to a storage device; writing the first block to a journal connected with the storage device; associating a first logical address of a group of logical addresses of the journal with a first physical address of the storage; associating the first physical address to an additional second logical address of the storage device, the second logical address not of the group of logical addresses of the journal; and disassociating the first physical address from the first logical address, in response to associating the first physical address with the additional second logical address.

Claims (33)

1. A computerized method for improved redundancy in storage devices, comprising:

receiving a first data block for writing to a storage device;

writing the first block to a journal connected with the storage device;

associating a first logical address of a group of logical addresses of the journal with a first physical address of the storage;

associating the first physical address to an additional second logical address of the storage device, the second logical address not of the group of logical addresses of the journal; and

disassociating the first physical address from the first logical address, in response to associating the first physical address with the additional second logical address;

wherein the storage device is one of a plurality of storage devices, comprising a first group of storage devices, and a second group of parity storage devices.

2. The computerized method of claim 1 , wherein the journal includes at least one of: a group of logical addresses of the storage device and a group of logical addresses on at least one other storage devices.

3. The computerized method of claim 1 , further comprising:

updating at least one parity blocks in at least one parity storage devices, in response to writing the first block, so that the updated one or more parity blocks are based at least in part on the first block.

4. The computerized method of claim 3 , wherein disassociating the first physical address from the first logical address is further in response to receiving a notification from a parity storage device of the second group, that the parity storage has been updated.

5. The computerized method of claim 1 , wherein each storage device of the first group is communicatively coupled with a journal, such that the journal of a first storage device is physically on a second storage device.

6. A computer readable medium having stored thereon instructions for causing processing circuitry to execute a process for improved redundancy in storage devices, the process comprising:

receiving a first data block for writing to a storage device;

writing the first block to a journal communicatively coupled with the storage device;

associating a first logical address of a group of logical addresses of the journal, with a first physical address of the storage;

associating the first physical address to an additional second logical address of the storage device, the second logical address not of the group of logical addresses of the journal; and

disassociating the first physical address from the first logical address, in response to associating the first physical address with the additional second logical address;

wherein the storage device is one of a plurality of storage devices, comprising a first group of storage devices, and a second group of parity storage devices.

7. A computing system for improving redundancy in storage devices, comprising:

a memory; and

a processing circuitry coupled to the memory, wherein the processing circuitry is configured to execute instructions stored on the memory to:

receive a first data block for writing to a storage device;

write the first block to a journal connected with the storage device;

associate a first logical address of a group of logical addresses of the journal, with a first physical address of the storage;

associate the first physical address to an additional second logical address of the storage device, the second logical address not of the group of logical addresses of the journal; and

disassociate the first physical address from the first logical address, in response to associating the first physical address with the additional second logical address;

wherein the storage device is one of a plurality of storage devices, comprising a first group of storage devices, and a second group of parity storage devices.

8. The computing system of claim 7 , wherein the journal is comprised of any of: a group of logical addresses of the storage device, a group of logical addresses on one or more other storage devices, and any combination thereof.

9. The computing system of claim 7 , wherein the processor is further configured to:

update at least one parity blocks in at least one parity storage devices, in response to writing the first block, so that the updated one or more parity blocks are based at least in part on the first block.

10. The computing system of claim 9 , wherein disassociating the first physical address from the first logical address is further in response to receiving a notification from a parity storage device of the second group, that the parity storage has been updated.

11. The computing system of claim 7 , wherein each storage device of the first group is connected with a journal, wherein the journal of a first storage device is physically on a second storage device.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2022
From: EXCELERO STORAGE LTD.
To: NVIDIA CORPORATION
Reel/Frame 059249/0950 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2018
From: ROMEM, YANIV; OSHRI, OFER; MANN, OMRI; SHOIKHET, KIRILL; HERMAN SHMULYAN, DANIEL; JACKSON, JAMES
To: EXCELERO STORAGE LTD.
Reel/Frame 047834/0085 →
Continuity (2)
Provisional Application 62610218 · Dec 24, 2017
Related Publication 20190196900A1 · Jun 27, 2019