Transfer circuit, shift register, gate driver, display panel, and flexible substrate
A transfer circuit includes an input circuit, a reset circuit, an output circuit, and an output stabilizer circuit, and obtains an input signal at an input terminal, holds the input signal, and outputs the input signal from an output terminal as an output signal in synchronization with a clock signal. The transfer circuit includes an inverter circuit that has an input terminal connected to at least one of the input and output terminals of the transfer circuit, and outputs, from an output terminal, an inverted signal having an inverted polarity of at least one of the input and output signals. The reset circuit includes a first transistor having a control signal end connected to the output terminal of the inverter circuit, the first transistor switching continuity and discontinuity of a signal path between one end of a first capacitor that holds the input signal and a first power supply.
1. A transfer circuit that includes an input circuit, a reset circuit, an output circuit, and an output stabilizer circuit, and obtains an input signal at an input terminal, holds the input signal, and outputs the input signal from an output terminal as an output signal in synchronization with a clock signal, the transfer circuit comprising:
a first capacitor that holds the input signal;
a first inverter circuit that has an input terminal connected to the input terminal of the transfer circuit, and outputs an inverted signal from an output terminal, the inverted signal having an inverted polarity of the input signal; and
a fourth transistor having a control signal end connected to the output terminal of the first inverter circuit, the fourth transistor switching continuity and discontinuity of a signal path between a first end of the first capacitor that holds the input signal and a first power supply,
wherein the first inverter circuit is included in the reset circuit.
2. The transfer circuit according to claim 1 , further comprising:
a second inverter circuit included in the output stabilizer circuit and having an input terminal connected to the output terminal of the transfer circuit, the second inverter circuit outputting, from an output terminal, an inverted signal having an inverted polarity of the output signal of the transfer circuit,
the control signal end of the first transistor is connected to the output terminal of the first inverter circuit, and
a second transistor included in the output stabilizer circuit and having a control signal end connected to the output terminal of the second inverter circuit, the second transistor switching continuity and discontinuity of a signal path between a second end of the first capacitor that holds the input signal and a second power supply.
3. The transfer circuit according to claim 2 , wherein
the output circuit includes the first capacitor and the first transistor,
the input circuit includes a third transistor, the third transistor switching continuity and discontinuity of a signal path between the input terminal of the transfer circuit and the control signal end of the first transistor, and
the reset circuit further includes a fifth transistor connected with the fourth transistor in series on the signal path between the first end of the first capacitor and the first power supply.
4. The transfer circuit according to claim 3 , further comprising:
a control terminal, for receiving a control signal, connected to a control signal end of the third transistor and a control signal end of the fifth transistor.
5. The transfer circuit according to claim 1 , wherein
the first inverter circuit includes:
a second capacitor connected to the input terminal of the inverter circuit;
a thirteenth transistor connected between a second power supply and the second capacitor;
an eleventh transistor connected between the output terminal of the inverter circuit and a third power supply; and
a twelfth transistor connected between the output terminal of the inverter circuit and a fourth power supply.
6. The transfer circuit according to claim 5 , wherein
the first inverter circuit outputs the inverted signal in synchronization with the clock signal of the transfer circuit.
7. The transfer circuit according to claim 1 , wherein
each transistor included in the transfer circuit is an oxide semiconductor transistor.
8. A shift register, comprising:
a plurality of transfer circuits connected in multiple stages, wherein
each of the plurality of transfer circuits in the multiple stages is the transfer circuit according to claim 1 .
9. A gate driver, comprising:
the shift register according to claim 8 ; and
a buffer circuit that processes an output signal from each of the multiple stages of the shift register.
10. A display panel comprising the gate driver according to claim 9 .
11. A flexible substrate comprising the gate driver according to claim 9 .
12. The transfer circuit according to claim 1 , further comprising:
a first transistor having a control signal end connected to the first end of the first capacitor, the first transistor switching continuity and discontinuity of a signal path between a pulse power supply and the output terminal of the transfer circuit, the first transistor being a depletion-type transistor having a negative threshold voltage.
13. A transfer circuit that includes an input circuit, a reset circuit, an output circuit, and an output stabilizer circuit, and obtains an input signal at an input terminal, holds the input signal, and outputs the input signal from an output terminal as an output signal in synchronization with a clock signal, the transfer circuit comprising:
a first capacitor that holds the input signal;
a second inverter circuit that has an input terminal connected to the output terminal of the transfer circuit, and outputs an inverted signal from an output terminal, the inverted signal having an inverted polarity of the output signal; and
a second transistor having a control signal end connected to the output terminal of the second inverter circuit, the second transistor switching continuity and discontinuity of a signal path between a second end of the first capacitor that holds the input signal and a first power supply,
wherein the second inverter circuit is included in the output stabilizer circuit.
14. The transfer circuit according to claim 13 , wherein
the output circuit includes the first capacitor and the first transistor,
the input circuit includes a third transistor, the third transistor switching continuity and discontinuity of a signal path between the input terminal of the transfer circuit and the control signal end of the first transistor, and
the reset circuit further includes a fifth transistor connected with a fourth transistor in series on a signal path between the first end of the first capacitor and a second power supply.
15. The transfer circuit according to claim 14 , wherein
a control signal applied to a control signal end of the third transistor and a control signal applied to a gate of the fifth transistor do not become high level simultaneously.
16. The transfer circuit according to claim 13 , further comprising:
a first transistor having a control signal end connected to a first end of the first capacitor, the first transistor switching continuity and discontinuity of a signal path between a pulse power supply and the output terminal of the transfer circuit, the first transistor being a depletion-type transistor having a negative threshold voltage.
17. The transfer circuit according to claim 13 , wherein
the second inverter circuit includes:
a second capacitor connected to the input terminal of the inverter circuit;
a twenty-third transistor connected between a second power supply and the second capacitor;
a twenty-first transistor connected between the output terminal of the inverter circuit and a third power supply; and
a twenty-second transistor connected between the output terminal of the inverter circuit and a fourth power supply.
18. The transfer circuit according to claim 17 , wherein
the second inverter circuit outputs the inverted signal in synchronization with the clock signal of the transfer circuit.
19. The transfer circuit according to claim 13 , wherein
each transistor included in the transfer circuit is an oxide semiconductor transistor.
20. A shift register, comprising:
a plurality of transfer circuits connected in multiple stages, wherein
each of the plurality of transfer circuits in the multiple stages is the transfer circuit according to claim 13 .