Time slicing method for multi-channel color tuning using a single current source input

1. A system comprising:

a memory configured to store instructions; and

a hardware-based processor configured to execute the instructions to cause the system to perform operations comprising:

determine a pulse-width modulation (PWM) frequency of an input PWM signal,

generate a first PWM signal for a first light emitting diode (LED), a second PWM signal for a second LED, and a third PWM signal for a third LED, such that each of the first PWM signal, the second PWM signal, and the third PWM signal has the PWM frequency and is in phase with the input PWM signal,

vary a first duty cycle of the first PWM signal, a second duty cycle of the second PWM signal, and a third duty cycle of the third PWM signal based on a control signal, such that a sum of the first duty cycle, the second duty cycle, and the third duty cycle is a predetermined percentage, and

select values of the first duty cycle, the second duty cycle, and the third duty cycle from a table in the memory based on the control signal.

2. The system of claim 1 , wherein the determining the PWM frequency of the input PWM signal comprises:

measuring a difference in time between an interrupt for a rising edge of the input PWM signal and an interrupt for a falling edge of the input PWM signal.

3. The system of claim 1 , wherein the sum of the first duty cycle, the second duty cycle, and the third duty cycle is 100%.

4. The system of claim 1 , wherein the control signal is generated by a control signal interface.

5. A system comprising:

a first light emitting diode (LED) configured to be powered using a first pulse-width modulated (PWM) signal;

a second LED configured to be powered using a second PWM signal;

a third LED configured to be powered using a third PWM signal;

a memory configured to store instructions; and

a hardware-based processor configured to execute the instructions to cause the system to perform operations comprising:

determine a PWM frequency of an input PWM signal,

generate the first PWM signal, the second PWM signal, and the third PWM signal, such that each of the first PWM signal, the second PWM signal, and the third PWM signal has the PWM frequency and is in phase with the input PWM signal,

vary a first duty cycle of the first PWM signal, a second duty cycle of the second PWM signal, and a third duty cycle of the third PWM signal based on a control signal, such that a sum of the first duty cycle, the second duty cycle, and the third duty cycle is a predetermined percent, and

select values of the first duty cycle, the second duty cycle, and the third duty cycle from a configured table based on the control signal.

6. The system of claim 5 , wherein the determining the PWM frequency of the input PWM signal comprises:

measuring a difference in time between an interrupt for a rising edge of the input PWM signal and an interrupt for a falling edge of the input PWM signal.

7. The system of claim 5 , wherein the hardware-based processor is further configured to execute the instructions to cause the system to:

vary duty cycles such that the sum of the first duty cycle, the second duty cycle, and the third duty cycle is 100%.

8. The system of claim 5 , wherein the control signal is generated by a control signal interface.

9. The system of claim 5 , further comprising:

a current source configured to provide a driving current to the first LED, the second LED, and the third LED; and

a sensing circuit configured to receive the driving current and provide the input PWM signal to the hardware-based processor.

10. The system of claim 9 , wherein the sensing circuit comprises a Zener diode and a capacitive divider.

11. The system of claim 9 , further comprising a buffer located between the sensing circuit and the hardware-based processor.

12. The system of claim 9 , further comprising:

a low pass filter coupled to the current source and the sensing circuit.

13. The system of claim 12 , wherein the sensing circuit comprises a Zener diode and a capacitive divider.

14. The system of claim 12 , wherein the low pass filter comprises a resistor and a capacitor.

15. The system of claim 1 , wherein the table contains a plurality of user input values, each user input value associated with a different combination of to the first duty cycle, the second duty cycle and the third duty cycle.

16. The system of claim 15 , wherein each user input value is at least one type of parameter selected from parameters including a user-set color temperature and a brightness level.

17. The system of claim 1 , wherein the hardware-based processor is further configured to:

set a rising interrupt for a rising edge of the input PWM signal at an input voltage terminal and a falling interrupt for a falling edge of the input PWM signal at the input voltage terminal,

start a timer when the rising interrupt is tripped and stop the timer when the falling interrupt is tripped,

produce, based on the timer, a clock count of a high period of the input PWM signal,

calculate a first pulse width of the input PWM signal at the input voltage terminal based on the clock count, and

use the calculation of the first pulse width to determine the PWM frequency of the input PWM signal.

18. The system of claim 17 , wherein the hardware-based processor is further configured to use a determination of the PWM frequency of the input PWM signal to adapt the PWM frequency of the first PWM signal, the second PWM signal, and the third PWM signal and synchronize a phase of the first PWM signal, the second PWM signal, and the third PWM signal to a phase of the first PWM signal at the input voltage terminal.

19. The system of claim 17 , wherein the hardware-based processor is further configured to:

measure a PWM cycle of the input PWM signal in a first cycle,

perform processing and timing calculations of the input PWM signal in a second cycle, and

alter at least one of the first PWM signal, the second PWM signal, and the third PWM signal in a third cycle.

20. The system of claim 17 , wherein the hardware-based processor is further configured to:

use a leading offset to compensate for a rise time of the rising edge of the input PWM signal and an interrupt delay to permit routing of power to one of the first PWM signal, the second PWM signal, and the third PWM signal at a beginning of each PWM cycle.