Memory system and processor system
A memory system connected to a processor is described. The memory system includes a volatile first storage section, a nonvolatile second storage section having a smaller storage capacity than that of the first storage section, and a storage control section that performs control to store data sets in the second storage section. Each of the data sets including data written in the first storage section in response to a write command from the processor, address information indicating a write destination in the first storage section, and address information indicating a write destination in a nonvolatile third storage section to which the data written in the first storage section is to be written back.
1. A memory system connectable to a processor, the memory system comprising:
a volatile first storage section;
a nonvolatile second storage section having a smaller storage capacity than that of the first storage section;
a storage controller configured to control to store data sets in the second storage section, each of the data sets including data written in the first storage section in response to a write command from the processor, address information indicating a write destination in the first storage section, and address information indicating a write destination in a nonvolatile third storage section to which the data written in the first storage section is to be written back;
a nonvolatile fourth storage section that stores at least some of the data sets stored in the second storage section,
wherein when the data in the first storage section is lost before the data in the first storage section is written back to the third storage section, the storage controller is configured to write back the data sets stored in the second storage section to the fourth storage section.
2. The memory system according to claim 1 , wherein when the data in the first storage section is lost before the data in the first storage section is written back to the third storage section, the storage controller is configured to write the data to be written back to the third storage section based on the data sets stored in the second storage section.
3. The memory system according to claim 2 , wherein each of the data sets further includes attribute information of data written in the first storage section, and the storage controller performs control to store the data sets in each of the second storage sections.
4. The memory system according to claim 2 , wherein the write latency to the second storage section is 100 ns or less.
5. The memory system according to claim 1 , further comprising a first member on which the first storage section, the second storage section, and the storage controller are mounted,
wherein the third storage section is provided in a second member separate from the first member.
6. The memory system according to claim 1 , further comprising a nonvolatile fourth storage section that stores at least some of the data sets stored in the second storage section,
wherein the storage controller is configured to perform control to store at least some of the data sets stored in the second storage section in the fourth storage section during a period from the execution of a write command to the execution of a next write command by the processor, and to permit overwriting of data sets stored in the fourth storage section among the data sets stored in the second storage section.
7. The memory system according to claim 6 , further comprising: a first member on which the first storage section, the second storage section, the fourth storage section, and the storage controller are mounted,
wherein the third storage section is provided in a second member separate from the first member.
8. The memory system according to claim 6 , wherein the writing speed to the second storage section is higher than the writing speed to the fourth storage section, and
wherein the fourth storage section has a smaller storage capacity than that of the third storage section and the fourth storage section has a larger storage capacity than that of the second storage section.
9. The memory system according to claim 6 , wherein the storage controller is configured to write the data to be written back to the third storage section based on the data sets written in the fourth storage section.
10. The memory system according to claim 1 , further comprising:
a first member on which the first storage section is mounted; and
a second member on which the second storage section, the fourth storage section, and the storage controller are mounted,
wherein the third storage section is provided in a third member separate from the first member and the second member.
11. The memory system according to claim 1 , wherein the writing speed to the second storage section is higher than the writing speed to the fourth storage section.
12. The memory system according to claim 1 , wherein the storage controller is configured to write the data to be written back to the third storage section based on the data sets written in the fourth storage section.
13. The memory system according to claim 1 , further comprising:
a plurality of first members on each of which the first storage section is mounted; and
a second member on which a plurality of the second storage sections each of which stores the data sets corresponding to the first storage section mounted on each of the plurality of first members, and the storage controller are mounted,
wherein the third storage section is provided in a third member separate from the first members and the second member.
14. The memory system according to claim 1 , wherein each of the data sets further includes attribute information of data to be written or already written in the first storage section, and the storage controller performs control to store the data sets in each of the second storage sections.
15. The memory system according to claim 1 , wherein the write latency to the second storage section is 100 ns or less.
16. The memory system according to claim 1 , wherein the second storage section is an MRAM (Magnetoresistive Random Access Memory).
17. The memory system according to claim 1 , wherein a DIMM (Dual Inline Memory Module) on which the first storage section, the second storage section, and the storage controller are mounted is provided.
18. A processor system, comprising:
a processor; and
a memory system accessed by the processor;
wherein the memory system includes:
a volatile first storage section;
a nonvolatile second storage section having a smaller storage capacity than that of the first storage section;
a storage controller that performs control to store data sets in the second storage section, each of the data sets including data written in the first storage section in response to a write command from a processor, address information indicating a write destination in the first storage section, and address information indicating a write destination in a nonvolatile third storage section to which the data written in the first storage section is to be written back; and
a nonvolatile fourth storage section that stores at least some of the data sets stored in the second storage section,
wherein when the data in the first storage section is lost before the data in the first storage section is written back to the third storage section, the storage controller is configured to write back the data sets stored in the second storage section to the fourth storage section.