System and method of interfacing co-processors and input/output devices via a main memory system
A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.
1. A memory module comprising:
one or more memory devices; and
control logic coupled to the one or more memory devices, the control logic comprising:
a host interface logic configured to receive a command from a host system coupled to the memory module;
a command buffer to store the command received from the host system, wherein the command buffer is allocated from a pool of command buffers in the memory module;
a buffer check logic configured to determine whether the command is complete; and
a memory interface logic configured to provide the command from the command buffer to at least one of the one or more memory devices in response to the command being complete.
2. The memory module of claim 1 , wherein the control logic further comprises a data buffer for storing data associated with the command.
3. The memory module of claim 1 , wherein the control logic further comprises a command buffer entry, and wherein the command buffer comprises a first field that specifies an entry point of the command within the command buffer entry.
4. The memory module of claim 1 , wherein the control logic further comprises an error correction code (ECC) circuit configured to validate the command received from the host system.
5. The memory module of claim 1 , wherein the control logic further comprises a data interleave circuit.
6. The memory module of claim 1 , wherein the control logic further comprises a data swizzle circuit.
7. The memory module of claim 1 , wherein the buffer check logic is configured to read one or more bits from each portion of a plurality of portions of the command and to determine that the one or more bits read from each portion together match a predetermined pattern.
8. The memory module of claim 1 , wherein the buffer check logic is configured to read a first bit and a second bit from each portion of a plurality of portions of the command and to determine that the first bit read from each portion is a non-zero value and the second bit read from each portion is a zero value.
9. The memory module of claim 1 , wherein the control logic further comprises a write buffer entry, and wherein for a write command, the host interface logic is configured to receive data associated with the write command from the host system and the write buffer entry is configured to store the data associated with the write command.
10. The memory module of claim 9 , wherein the write buffer entry has an associated vector indicating that a cache line of the write buffer entry is written at least once.
11. The memory module of claim 9 , wherein the command buffer comprises a second field that specifies a second entry point within the write buffer entry, and wherein the second entry point is associated with the data associated with the write command.
12. The memory module of claim 11 , wherein:
the command buffer comprises a third field that specifies a checksum associated with the data associated with the write command; and
the buffer check logic is configured to use the checksum specified in the third field to perform a checksum verification on data pulled from the write buffer entry at the second entry point specified in the second field to verify that all of the data associated with the write command has been written to the write buffer entry.
13. The memory module of claim 9 , wherein the write command and the data associated with the write command are interleaved in the write buffer entry.
14. The memory module of claim 1 , wherein the control logic further comprises a command processor configured to generate a direct memory access (DMA) descriptor based on the command and to communicate the DMA descriptor to the at least one of the one or more memory devices via the memory interface logic.
15. A co-processing or input/output (CPIO) module comprising:
one or more CPIO devices; and
control logic coupled to the one or more CPIO devices, the control logic comprising:
a host interface logic configured to receive a command from a host system coupled to the CPIO module;
a command buffer to store the command received from the host system, wherein the command buffer is allocated from a pool of command buffers in the memory module;
a buffer check logic configured to determine whether the command is complete; and
a CPIO interface logic configured to provide the command from the command buffer to at least one of the one or more CPIO devices in response to the command being complete.
16. The CPIO module of claim 15 , wherein the control logic further comprises a data buffer for storing data associated with the command.
17. The CPIO module of claim 15 , wherein the control logic further comprises a command buffer entry, and wherein the command buffer comprises a first field that specifies an entry point of the command within the command buffer entry.
18. The CPIO module of claim 15 , wherein the control logic further comprises at least one of an error correction code (ECC) circuit, a data interleave circuit, or a data swizzle circuit.
19. The memory module of claim 15 , wherein the buffer check logic is configured to read one or more bits from each portion of a plurality of portions of the command and to determine that the one or more bits read from each portion together match a predetermined pattern.
20. The CPIO module of claim 15 , wherein the control logic further comprises a command processor configured to generate a direct memory access (DMA) descriptor based on the command and to communicate the DMA descriptor to the at least one of the one or more CPIO devices via the CPIO interface logic.