System and method for facilitating differentiated error correction in high-density flash devices
Embodiments described herein provide a system for facilitating modulation-assisted error correction. The system can include a plurality of flash memory cells, an organization module, a mapping module, and a modulation module. During operation, the organization module groups bits of a cluster of cells in the plurality of flash memory cells into a first group and a second group. A respective of the first and second groups includes bits from a respective cell of the cluster of cells. The mapping module generates a modulation map that maps a subset of bits indicated by the first group in such a way that the subset of bits is repeated in a respective domain of bits indicated by the second group. The modulation module then programs user data bits in the cluster of cells based on the modulation map.
1. An apparatus, comprising:
a plurality of flash memory cells;
an organization module configured to group bits of a cluster of cells in the plurality of flash memory cells into a first group and a second group, wherein a respective of the first and second groups includes bits from a respective cell of the cluster of cells;
a mapping module configured to generate a modulation map that maps a subset of bits indicated by the first group in such a way that the subset of bits is repeated in a respective domain of bits indicated by the second group; and
a modulation module configured to program user data bits in the cluster of cells based on the modulation map.
2. The apparatus of claim 1 , wherein a number of dimensions of the modulation map corresponds to the number of cells in the cluster, and wherein a respective dimension of the modulation map corresponds to a voltage level of a cell of the cluster.
3. The apparatus of claim 2 , wherein programming the user data bits further comprises:
determining a point corresponding to the user data bits in the modulation map; and
programming the voltage level of a respective cell in the cluster based on the point.
4. The apparatus of claim 1 , further comprising an error-correction module configured to apply a first error-correction coding (ECC) to a first subset of bits of the user data bits that are modulated for the first group and a second ECC to a second subset of bits of the user data bits that are modulated for the second group, wherein the first ECC is configured to detect and correct a higher bit error rate than that of the second ECC.
5. The apparatus of claim 4 , wherein the modulation module is further configured to read the first subset of bits from the cluster of cells based on the first ECC, wherein the programmed voltage levels have become overlapping due to data retention over a period of time.
6. The apparatus of claim 4 , wherein the first ECC is configured to generate a first set of parity bits for the first subset of bits and the second ECC is configured to generate a second set of parity bits for the second subset of bits, and wherein the number of bits in the second set of parity bits is lower than that of the first set of parity bits.
7. The apparatus of claim 6 , further comprising a plurality of out-of-band (OOB) flash memory cells distinct from the plurality of flash memory cells;
wherein the modulation module is further configured to program one or more cells of the plurality of the OOB flash memory cells to store the first and second sets of parity bits.
8. The apparatus of claim 7 , wherein the modulation module is further configured to:
switch from the first ECC to a third ECC in response to determining a bit error rate higher than the capability of the first ECC;
apply the third ECC to the first subset of bits of the user data bits to generate a third set of parity bits for the first subset of bits; and
store an overflow bit of the third set of parity bits in an empty bit in a cell of the OOB flash memory cells.
9. The apparatus of claim 1 , wherein a respective cell of the plurality of flash memory cells is one of: a triple-level cell (TLC) and a quad-level cell (QLC), and wherein the cluster of cells includes at least two cells.
10. The apparatus of claim 1 , wherein the modulation map is a two-dimensional map, wherein voltage levels of the first cell of the cluster of cells indicate an x axis of the modulation map and voltage levels of the second cell of the cluster of cells indicate a y axis of the modulation map.
11. A control system of a flash memory device, comprising:
interface circuitry configured to communicate with a plurality of flash memory cells of the flash memory device; and
control circuitry configured to:
group bits of a cluster of cells in the plurality of flash memory cells into a first group and a second group, wherein a respective of the first and second groups includes bits from a respective cell of the cluster of cells;
generate a modulation map that maps a subset of bits indicated by the first group in such a way that the subset of bits is repeated in a respective domain of bits indicated by the second group; and
program user data bits in the cluster of cells based on the modulation map via the interface circuitry.
12. The control system of claim 11 , wherein a number of dimensions of the modulation map corresponds to the number of cells in the cluster, and wherein a respective dimension of the modulation map corresponds to a voltage level of a cell of the cluster.
13. The control system of claim 12 , wherein programming the user data bits further comprises:
determining a point corresponding to the user data bits in the modulation map; and
programming the voltage level of a respective cell in the cluster based on the point.
14. The control system of claim 11 , wherein the control circuitry is further configured to apply a first error-correction coding (ECC) to a first subset of bits of the user data bits that are modulated for the first group and a second ECC to a second subset of bits of the user data bits that are modulated for the second group, wherein the first ECC is configured to detect and correct a higher bit error rate than that of the second ECC.
15. The control system of claim 14 , wherein the control circuitry is further configured to read the first subset of bits from the cluster of cells based on the first ECC, wherein the programmed voltage levels have become overlapping due to data retention over a period of time.
16. The control system of claim 14 , wherein the first ECC is configured to generate a first set of parity bits for the first subset of bits and the second ECC is configured to generate a second set of parity bits for the second subset of bits, and wherein the number of bits in the second set of parity bits is lower than that of the first set of parity bits.
17. The control system of claim 16 , wherein the flash memory device further comprises a plurality of out-of-band (OOB) flash memory cells distinct from the plurality of flash memory cells; and
wherein the control circuitry is further configured to program one or more cells of the plurality of the OOB flash memory cells to store the first and second sets of parity bits.
18. The control system of claim 17 , wherein the control circuitry is further configured to:
switch from the first ECC to a third ECC in response to determining a bit error rate higher than the capability of the first ECC;
apply the third ECC to the first subset of bits of the user data bits to generate a third set of parity bits for the first subset of bits; and
store an overflow bit of the third set of parity bits in an empty bit in a cell of the OOB flash memory cells.
19. The control system of claim 11 , wherein a respective cell of the plurality of flash memory cells is one of: a triple-level cell (TLC) and a quad-level cell (QLC), and wherein the cluster of cells includes at least two cells.
20. The control system of claim 11 , wherein the modulation map is a two-dimensional map, wherein voltage levels of the first cell of the cluster of cells indicate an x axis of the modulation map and voltage levels of the second cell of the cluster of cells indicate a y axis of the modulation map.