IP Library Granted Patent US 11,264,780
Granted Patent B2
US 11,264,780 · App. 16/239,083 · Granted Mar 1, 2022

Flip chip backside emitting VCSEL package

Inventor: Yi-Ching Pao (Sunnyvale, CA)
Assignee: OEPIC SEMICONDUCTORS, INC.
H01S5/04254H01S5/0234H01S5/0237H01S5/02469H01S5/18305H01S5/18344H01S5/323H01S5/423H01S5/026H01S5/02345H01S5/04257
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,264,780
App. No.
16/239,083
Granted
Mar 1, 2022
Kind
B2
Abstract

A flip chip backside Vertical Cavity Surface Emitting Laser (VCSEL) package has a VCSEL pillar array. A first metal contact is formed over a top section of each pillar of the VCSEL pillar array. A second metal contact is formed on a back surface of the VCEL pillar array. An opening is formed in the second metal contact and aligned with the pillars of the VCSEL pillar array. Solder tip is applied on each pillar of the VCSEL pillar array to flip chip mount the VCSEL pillar array.

Claims (36)

1. A flip chip backside Vertical Cavity Surface Emitting Laser (VCSEL) package comprising:

a substrate;

a VCSEL pillar array formed on the substrate;

a first metal contact formed over a top section of each pillar of the VCSEL pillar array;

a second metal contact formed on a back surface of the substrate;

an opening formed in the second metal contact and aligned with the pillars of the VCSEL pillar array;

a plurality of third metal contacts formed around a perimeter of the VCSEL pillar array;

a plurality of plated vias formed around a perimeter of the VCSEL pillar array and through the substrate forming the VCSEL pillar array, the plurality of plated vias electrically connecting the second metal contact to the third metal contact; and

solder tip applied on each pillar of the VCSEL pillar array to flip chip mount the VCSEL pillar array.

2. The flip chip backside VCSEL package of claim 1 , comprising a plurality of wrap around connections formed around a perimeter of the VCSEL pillar array, wherein each of the wrap around connections is applied to a side surface of the VCSEL pillar array and electrically connects the second metal contact to one of the plurality of third metal contacts.

3. The flip chip backside VCSEL package of claim 1 , wherein at least one of the third metal contacts is electrically coupled to the second metal contact through one of the plurality of vias, wherein the third metal contacts are of a same height as each of the first contacts.

4. The flip chip backside VCSEL package of claim 1 , comprising a substrate package having a plurality of substrate package metal contacts, the VCSEL pillar array flip chip mounted to the substrate package so the first metal contact formed over a top section of each pillar of the VCSEL pillar array is coupled to one of the plurality of substrate package metal contacts.

5. The flip chip backside VCSEL package of claim 4 , wherein the substrate package is of a same length of the VCSEL array.

6. The flip chip backside VCSEL package of claim 4 , wherein the substrate package is a heat sink.

7. A flip chip backside Vertical Cavity Surface Emitting Laser (VCSEL) package comprising:

a substrate

a VCSEL pillar array formed on the substrate;

a first metal contact formed over a top section of each pillar of the VCSEL pillar array;

a second metal contact formed on a back surface of the VCSEL pillar array;

an opening formed in the second metal contact and aligned with the pillars of the VCSEL pillar array;

a plurality of third metal contacts formed around a perimeter of the VCSEL pillar array;

a plurality of plated vias formed around a perimeter of the VCSEL pillar array and through the substrate electrically connecting at least one of the second metal contact to the third metal contact;

a substrate package having a plurality of substrate package metal contacts, the VCSEL pillar array flip chip mounted to the substrate package forming a backside illuminating VCSEL array, wherein the first metal contact formed over a top section of each pillar of the VCSEL pillar array is coupled to one of the plurality of substrate package metal contacts; and

solder applied on each pillar of the VCSEL pillar array to flip chip mount the VCSEL pillar array to the substrate package.

8. The flip chip backside VCSEL package of claim 7 , comprising a plurality of wrap around connections formed around a perimeter of the VCSEL pillar array, the plurality of wrap around connections applied to side surfaces of the VCSEL pillar array and electrically connecting the second metal contact to one of the plurality of third metal contacts.

9. The flip chip backside VCSEL package of claim 7 , wherein the plurality of third metal contacts are of a same height as each of the first contacts.

10. The flip chip backside VCSEL package of claim 7 , wherein the substrate package is of a same length of the VCSEL array.

11. A method of forming a flip chip backside Vertical Cavity Surface Emitting Laser (VCSEL) package comprising:

forming a VCSEL pillar array on a substrate;

applying a first metal contact over a top section of each pillar of the VCSEL pillar array;

applying a second metal contact formed on a back surface of the substrate, wherein an opening is formed in the second metal contact and aligned with the pillars of the VCSEL pillar array;

applying a plurality of third metal contacts around a perimeter of the VCSEL pillar array;

forming a plurality of plated vias around a perimeter of the VCSEL pillar array and through the substrate electrically connecting at least one of the second metal contact to one of the plurality of third metal contacts; and

applying solder on each pillar of the VCSEL pillar array to flip chip mount the VCSEL pillar array to a substrate package, wherein the substrate package has a plurality of substrate package metal contacts, the VCSEL pillar array flip chip mounted to the substrate package forming a backside illuminating VCSEL array, wherein the first metal contact formed over a top section of each pillar of the VCSEL pillar array is coupled to one of the plurality of substrate package metal contacts.

12. The method of claim 11 , comprising forming a plurality of wrap around connections around a perimeter of the VCSEL pillar array, the plurality of wrap around connections applied to side surfaces of the VCSEL pillar array and electrically connecting the second metal contact to the third metal contact.

13. The method of claim 11 , wherein the third metal contacts are of a same height as each of the first contacts.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2025
From: PATENT SAFE
To: NETFORCE OELABS, INC.
Reel/Frame 072122/0485 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 065557 FRAME 0695. ASSIGNOR(S) HEREBY CONFIRMS THE FOR PATENT SAFE, INC. Recorded Nov 20, 2023
From: OEPIC SEMICONDUCTORS, INC
To: PATENT SAFE, INC.
Reel/Frame 065631/0185 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2023
From: OEPIC SEMICONDUCTORS, INC
To: FOR PATENT SAFE, INC.
Reel/Frame 065557/0695 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2022
From: PAO, YI-CHING
To: OEPIC SEMICONDUCTORS, INC.
Reel/Frame 058696/0687 →
Continuity (2)
Provisional Application 62622668 · Jan 26, 2018
Related Publication 20190237931A1 · Aug 1, 2019