Increasing storage areal density using predictive data locations
Disclosed are systems, methods, and devices for increasing the storage areal density of a storage device. In one embodiment, a method is disclosed comprising receiving host data, the host data including first data and extra bit data; generating run-length limited (RLL) data by encoding the first data with an RLL encoder; generating a symbol corresponding to at least one bit of the extra bit data; and generating superpositioned data by inserting the symbol within a contiguous section of repeating bits in the RLL-encoded first data.
1. A method comprising:
receiving, by a processor, first data and second data;
encoding, by the processor, the first data to generate encoded data;
generating, by the processor, a symbol corresponding to the second data; and
generating, by the processor, superpositioned data by inserting the symbol within the encoded data.
2. The method of claim 1 , the receiving first data and second data comprising receiving the first data and second data as a bitstream.
3. The method of claim 1 , the encoding the first data comprising encoding the first data such that the encoded data limits the length of any continuous run of zeros to be within a predefined range.
4. The method of claim 1 , the encoding the first data comprising encoding the first data using a run-length limited (RLL) encoder.
5. The method of claim 1 , the encoding the first data comprising encoding the first data using a maximum transition run (MTR) encoder.
6. An apparatus comprising:
one or more processors; and
a non-transitory memory storing computer-executable instructions therein that, when executed by the processor, cause the apparatus to perform the operations of:
receiving first data and second data;
encoding the first data to generate encoded data;
generating a symbol corresponding to the second data; and
generating superpositioned data by inserting the symbol within the encoded data.
7. The apparatus of claim 6 , the receiving first data and second data comprising receiving the first data and second data as a bitstream.
8. The apparatus of claim 6 , the encoding the first data comprising encoding the first data such that the encoded data limits the length of any continuous run of zeros to be within a predefined range.
9. The apparatus of claim 6 , the encoding the first data comprising encoding the first data using a run-length limited (RLL) encoder.
10. The apparatus of claim 6 , the encoding the first data comprising encoding the first data using a maximum transition run (MTR) encoder.
11. A method comprising:
receiving, by a processor, data, the data including at least one codeword;
locating, by the processor, extra bits included in the codeword using a pre-defined preamble pattern;
demodulating, by the processor, the extra bits to generate an extra bit portion; and
replacing, by the processor, the extra bits in the codeword with the extra bit portion to obtain a second codeword.
12. The method of claim 11 , the receiving data comprising reading a hard disk drive sector storing the data.
13. The method of claim 11 , further comprising descrambling the data to identify the codeword.
14. The method of claim 11 , further comprising decoding the codeword using an error-code correction (ECC) code.
15. The method of claim 11 , the locating the extra bits included in the codeword using the pre-defined preamble pattern further comprising locating the extra bits included in the codeword using the pre-defined postamble pattern.
16. The method of claim 11 , the locating the extra bits included in the codeword using the pre-defined preamble pattern comprising identifying a repeating pattern of zeros in the codeword, the pattern of zeros representing an invalid sequence in the codeword.
17. The method of claim 11 , the locating the extra bits included in the codeword using the pre-defined preamble pattern comprising extracting two bits after the preamble pattern.
18. The method of claim 11 , further comprising sequencing the extra bits based on an index of the extra bits in a sequence.
19. The method of claim 11 , the demodulating the extra bits to generate the extra bit portion comprising converting a two-bit sequence in the extra bits to a single bit.
20. The method of claim 11 , further comprising decoding the second codeword using an encoder selected from the group consisting of a run-length limited (RLL) encoder and a maximum transition run (MTR) encoder.
21. The method of claim 20 , further comprising performing, by the processor, a cyclical redundancy check (CRC) on the decoded second codeword.
22. An apparatus method comprising:
one or more processors; and
a non-transitory memory storing computer-executable instructions therein that, when executed by the processor, cause the apparatus to perform the operations of:
receiving data, the data including at least one codeword;
locating extra bits included in the codeword using a pre-defined preamble pattern;
demodulating the extra bits to generate an extra bit portion; and
replacing the extra bits in the codeword with the extra bit portion to obtain a second codeword.
23. The apparatus of claim 22 , the receiving data comprising reading a hard disk drive sector storing the data.
24. The apparatus of claim 22 , further comprising descrambling the data to identify the codeword.
25. The apparatus of claim 22 , further comprising decoding the codeword using an error-code correction (ECC) code.
26. The apparatus of claim 22 , the locating the extra bits included in the codeword using the pre-defined preamble pattern further comprising locating the extra bits included in the codeword using the pre-defined postamble pattern.
27. The apparatus of claim 22 , the locating the extra bits included in the codeword using the pre-defined preamble pattern comprising identifying a repeating pattern of zeros in the codeword, the pattern of zeros representing an invalid sequence in the codeword.
28. The apparatus of claim 22 , the locating the extra bits included in the codeword using the pre-defined preamble pattern comprising extracting two bits after the preamble pattern.
29. The apparatus of claim 22 , further comprising sequencing the extra bits based on an index of the extra bits in a sequence.
30. The apparatus of claim 22 , the demodulating the extra bits to generate the extra bit portion comprising converting a two-bit sequence in the extra bits to a single bit.
31. The apparatus of claim 22 , the instructions further causing the apparatus to perform the operation of decoding the second codeword using an encoder selected from the group consisting of a run-length limited (RLL) encoder and a maximum transition run (MTR) encoder.
32. The apparatus of claim 31 , the instructions further causing the apparatus to perform the operation of performing a cyclical redundancy check (CRC) on the decoded second codeword.