Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses

1. A method for fabricating at least one component unfavorably sensitive to compressive stress, comprising:

producing, in a semiconductor substrate, an insulating region delimiting an active region of the semiconductor substrate;

producing at least one component unfavorably sensitive to compressive stress at least partially in the active region, wherein the at least one component unfavorably sensitive to compressive stress is an NMOS transistor belonging to a control unit of a memory plane of an integrated memory device, the memory plane having nonvolatile memory cells and selection transistors with buried gates; and

forming at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region;

wherein forming the at least one electrically inactive trench is carried out simultaneously with forming the buried gates.

2. The method according to claim 1 , further comprising:

producing, above the at least one component unfavorably sensitive to compressive stress, the active region and the insulating region, an additional insulating region comprising an insulating lower layer in compression; and

producing at least one contact region arranged above at least a part of the trench and below the insulating lower layer in compression;

wherein producing of the at least one contact region is carried out simultaneously with the production of contacts on source, drain and gate regions of transistors of the memory device.

3. The method according to claim 1 , further comprising forming first trenches for the buried gates and forming a second trench for the at least one electrically inactive trench, and wherein forming the first trenches and forming the second trench are performed simultaneously.

4. A method, comprising:

producing a memory cell supported by a semiconductor substrate in a memory plane region of an integrated circuit, wherein producing the memory cell comprises forming a selection transistor by:

etching a first trench in semiconductor substrate; and

filling the first trench with an insulated conductive material that forms a buried gate for the selection transistor; and

producing a control circuit for the memory cell by:

forming an insulating region in the semiconductor substrate that delimits an active region; and

producing at least one circuit component of the control circuit which is unfavorably sensitive to compressive stress at least partially in the active region;

forming a second trench in the insulating region; and

filling the second trench with an insulated conductive material that forms an electrically inactive trench, said insulated conductive material configured to reduce compressive stress in the active region;

wherein etching the first trench and etching the second trench are performed simultaneously.

5. The method according to claim 4 , wherein filling the first trench and filling the second trench are performed simultaneously.

6. The method according to claim 4 , further comprising:

producing contacts on source, drain and gate regions of transistors of the memory cell;

producing, above the at least one circuit component, the active region and the insulating region, an additional insulating region comprising an insulating lower layer in compression; and

producing, above at least a part of the trench and below the insulating lower layer in compression, at least one contact region for the at least one circuit component;

wherein producing contacts on source, drain and gate regions and producing the at least one contact region are performed simultaneously.