IP Library Granted Patent US 10,795,838
Granted Patent B2
US 10,795,838 · App. 16/242,471 · Granted Oct 6, 2020

Using transfer buffer to handle host read collisions in SSD

Inventors: Peng Li (Beaverton, OR); David J. Pelster (Longmont, CO); William Harper (Portland, OR)
Assignee: Intel Corporation
G06F13/1673G06F3/0604G06F3/0656G06F3/0679G06F12/06
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Quick Facts
Patent No.
US 10,795,838
App. No.
16/242,471
Granted
Oct 6, 2020
Kind
B2
Abstract

An embodiment of a semiconductor apparatus may include technology to detect a collision for a read request of an electronic storage device, and read data for the read request directly from a transfer buffer if the collision is detected. Other embodiments are disclosed and claimed.

Claims (49)

1. A semiconductor apparatus for use with an electronic storage device, comprising:

one or more substrates; and

logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the one or more substrates to:

detect a collision for a read request of an electronic storage device, wherein the detection of the collision is based on an exception flag in a logical-to-physical table entry which corresponds to the read request, and

read data for the read request directly from a transfer buffer if the collision is detected.

2. The apparatus of claim 1 , wherein the logic is further to:

determine an address to read from the transfer buffer based on the logical-to-physical table entry if the exception flag is set to represent an exception condition.

3. The apparatus of claim 1 , wherein the logic is further to:

increase a reference count for a cache slot indicated in the logical-to-physical table entry.

4. The apparatus of claim 1 , wherein the logic is further to:

detect an exception condition for a write request of an electronic storage device;

write data for the write request to a write address of the transfer buffer;

set an exception flag in a logical-to-physical table entry which corresponds to the write request to indicate the exception condition; and

update the logical-to-physical table entry to point to the write address of the transfer buffer.

5. The apparatus of claim 1 , wherein the electronic storage device comprises NAND media.

6. The apparatus of claim 1 , wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.

7. An electronic storage system, comprising:

a persistent storage media;

a transfer buffer; and

a controller communicatively coupled to the persistent storage media and the transfer buffer, the controller including logic to:

detect a collision for a read request, wherein the detection of the collision is based on an exception flag in a logical-to-physical table entry which corresponds to the read request, and

read data for the read request directly from the transfer buffer if the collision is detected.

8. The system of claim 7 , wherein the logic is further to:

determine an address to read from the transfer buffer based on the logical-to-physical table entry if the exception flag is set to represent an exception condition.

9. The system of claim 7 , wherein the logic is further to:

increase a reference count for a cache slot indicated in the logical-to-physical table entry.

10. The system of claim 7 , wherein the logic is further to:

detect an exception condition for a write request;

write data for the write request to a write address of the transfer buffer;

set an exception flag in a logical-to-physical table entry which corresponds to the write request to indicate the exception condition; and

update the logical-to-physical table entry to point to the write address of the transfer buffer.

11. The system of claim 7 , wherein the transfer buffer is located inside the controller.

12. A method of controlling storage, comprising:

detecting a collision for a read request of an electronic storage device, wherein the detection of the collision is based on an exception flag in a logical-to-physical table entry which corresponds to the read request; and

reading data for the read request directly from a transfer buffer if the collision is detected.

13. The method of claim 12 , further comprising:

determining an address to read from the transfer buffer based on the logical-to-physical table entry if the exception flag is set to represent an exception condition.

14. The method of claim 12 , further comprising:

increasing a reference count for a cache slot indicated in the logical-to-physical table entry.

15. The method of claim 12 , further comprising:

detecting an exception condition for a write request of an electronic storage device;

writing data for the write request to a write address of the transfer buffer;

setting an exception flag in a logical-to-physical table entry which corresponds to the write request to indicate the exception condition; and

updating the logical-to-physical table entry to point to the write address of the transfer buffer.

16. The method of claim 12 , further comprising:

writing data from the transfer buffer to a write address of NAND media of the electronic storage device;

setting an exception flag in a logical-to-physical table entry which corresponds to the data to indicate a non-exception condition; and

updating the logical-to-physical table entry to point to the write address of the NAND media.

17. The method of claim 12 , wherein the electronic storage device comprises a solid state drive.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2023
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP.
Reel/Frame 063815/0490 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 8, 2019
From: LI, PENG; PELSTER, DAVID J.; HARPER, WILLIAM
To: INTEL CORPORATION
Reel/Frame 047931/0593 →
Continuity (1)
Related Publication 20190138468A1 · May 9, 2019
Cited By (1)
US 12,669,964