IP Library Granted Patent US 10,749,069
Granted Patent B2
US 10,749,069 · App. 16/250,681 · Granted Aug 18, 2020

Solar cell and method for manufacturing the same

Inventors: Kwangsun Ji (Seoul, KR); Jin-won Chung (Seoul, KR); Yujin Lee (Seoul, KR)
Assignee: LG ELECTRONICS INC.
H01L31/1872H01L31/02167H01L31/0745H01L31/182H01L31/1804Y02E10/547Y02P70/521
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Quick Facts
Patent No.
US 10,749,069
App. No.
16/250,681
Granted
Aug 18, 2020
Kind
B2
Abstract

A method for manufacturing a solar cell, includes forming an oxide layer on first surface of a single crystalline silicon substrate; forming a poly crystalline silicon layer doped with a first dopant having a first conductive type on the oxide layer; diffusing a second dopant having a second conductive type opposite to the first conductive type into a second surface of the single crystalline silicon substrate thereby forming a diffusion region; forming a first passivation layer on the poly crystalline silicon layer; forming a second passivation layer on the diffusion region; forming a first electrode connected to the poly crystalline silicon layer by printing a first paste on the first passivation layer and firing through; forming a second electrode connected to the diffusion region by printing a second paste on the second passivation layer and firing through.

Claims (30)

1. A method for manufacturing a solar cell, the method comprising:

a layer forming operation of sequentially forming a tunnel layer formed of a dielectric material on a back surface of a semiconductor substrate including a single crystalline material, an intrinsic amorphous silicon layer on the tunnel layer by plasma enhanced chemical vapor deposition (PECVD), a dopant layer on the intrinsic amorphous silicon layer, and a capping layer on the dopant layer;

a thermal processing operation of, after forming the capping layer, through one successive thermal process being processing in a furnace, a recrystallization process for recrystallizing the intrinsic amorphous silicon layer into a polycrystalline silicon layer disposed on the tunnel layer, a diffusion process for diffusing an impurity of the dopant layer into the polycrystalline silicon layer, and forming a diffused region by diffusing an impurity at a front surface of the semiconductor substrate;

removing the capping layer after the thermal processing operation;

forming a hydrogen injection layer on the polycrystalline silicon layer on which the capping layer is removed after removing the capping layer;

applying a back electrode paste on the hydrogen injection layer to have a pattern after forming the hydrogen injection layer; and

forming a back electrode contacting with the polycrystalline silicon layer by penetrating through both the hydrogen injection layer and the dopant layer by a thermal processing after applying the back electrode paste.

2. The method according to claim 1 , wherein, in the forming the back electrode, hydrogen is supplied to the dopant layer and the tunnel layer.

3. The method according to claim 1 , wherein the tunnel layer includes one of silicon carbide (SiCx), silicon oxide (SiOx), silicon nitride (SiNx), hydrogenated silicon nitride (hydrogenated SiNx), aluminum oxide (AlOx), silicon oxynitride (SiOxNy), or hydrogenated silicon oxynitride (hydrogenated SiOxNy).

4. The method according to claim 1 , wherein the hydrogen injection layer is formed of a dielectric material.

5. The method according to claim 4 , wherein the hydrogen injection layer includes one of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon carbide (SiCx), or aluminum oxide (AlOx).

6. The method according to claim 1 , wherein the back electrode includes a plurality of finger electrodes, and a plurality of bus bars connected to the plurality of finger electrodes.

7. The method according to claim 1 , wherein the diffused region forms a front surface field region having a conductive type same as a conductive type of the semiconductor substrate.

8. The method according to claim 1 , wherein the diffused region is formed of a single crystalline silicon material same as the single crystalline material of the semiconductor substrate.

9. The method according to claim 1 , wherein the recrystallization process, the diffusion process, and the forming the diffused region are continuously performed by the thermal processing operation.

10. The method according to claim 1 , wherein the recrystallization process, an activation process of impurities of the polycrystalline silicon layer and the diffused region are continuously performed by the thermal processing operation.

11. The method according to claim 9 , wherein a temperature of the recrystallization process is lower than both a temperature of the diffusion process and a temperature of the forming the diffused region.

12. The method according to claim 9 , wherein the thermal processing operation includes a dehydrogenation process of dehydrogenating the intrinsic amorphous silicon layer.

13. The method according to claim 12 , wherein a temperature of the dehydrogenation process is lower than a temperature of the recrystallization process.

14. The method according to claim 1 , further comprising:

forming a passivation film on the diffused region;

applying a front electrode paste on the passivation film to have a pattern; and

forming a front electrode contacting with the diffused region by penetrating through the passivation film by a thermal processing after applying the front electrode paste.

15. The method according to claim 14 , wherein the forming the back electrode and the forming of the front electrode are performed by a same thermal processing.

16. The method according to claim 1 , wherein the diffused region is formed by using a gas including the impurity.

17. The method according to claim 1 , wherein the polycrystalline silicon layer forms an emitter layer including an impurity having a conductive type opposite to a conductive type of the semiconductor substrate.

18. The method according to claim 1 ,

wherein the back electrode paste contacts the hydrogen injection layer, the dopant layer and the polycrystalline silicon layer.

19. The method according to claim 1 , wherein the capping layer includes one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), or silicon carbide (SiCx).

20. The method according to claim 1 , wherein the dopant layer includes one of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon carbide (SiCx), or aluminum oxide (AlOx).

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2024
From: SHANGRAO XINYUAN YUEDONG TECHNOLOGY DEVELOPMENT CO. LTD.
To: TRINA SOLAR CO., LTD.
Reel/Frame 066831/0802 →
CHANGE OF NAME Recorded Dec 11, 2023
From: SHANGRAO JINKO SOLAR TECHNOLOGY DEVELOPMENT CO., LTD
To: SHANGRAO XINYUAN YUEDONG TECHNOLOGY DEVELOPMENT CO. LTD
Reel/Frame 066044/0299 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 28, 2022
From: LG ELECTRONICS INC.
To: SHANGRAO JINKO SOLAR TECHNOLOGY DEVELOPMENT CO., LTD
Reel/Frame 061571/0754 →
Priority Claims (1)
KR 10-2014-0152372 · Nov 4, 2014 · national
Continuity (2)
Continuation 14931591 · Nov 3, 2015
Related Publication 20190157495A1 · May 23, 2019