MINIMIZING RINGING IN WIDE BAND GAP SEMICONDUCTOR DEVICES
Embodiments include a power conversion circuit comprising first and second semiconductor switches, and a drive circuit configured to create a period of operational overlap for the first and second switches by setting a gate voltage of the first switch to an intermediate value above a threshold voltage of the first switch, during turn-on and turn-off operations of the second switch. Embodiments also include a method of operating first and second semiconductor devices, comprising: reducing a gate voltage of the first device to an intermediate value above a threshold voltage while the second device is off; turning off the first device after the second device is on; increasing the gate voltage of the first device to the intermediate value while the second device is on; and fully turning on the first device after the second device is off.
1 . A power conversion circuit, comprising:
a controller;
first and second power amplifiers electrically coupled to the controller;
a first semiconductor switch with a first gate electrically coupled to the first power amplifier;
a second semiconductor switch with a first gate electrically coupled to the second power amplifier, a current conducting path of the first semiconductor switch being in series with a current conducting path of the second semiconductor switch; and
wherein the controller is to, when controlling the second semiconductor switch to turn on and turn off, drive the first power amplifier to create a period of operational overlap for the first and second semiconductor switches by setting a gate voltage of the first semiconductor switch to an intermediate value above a threshold voltage of the first semiconductor switch.
2 . The power conversion circuit of claim 1 , wherein to create the period of operational overlap, the controller is to:
at a first time, set the gate voltage of the first semiconductor switch to the intermediate value; and
at a second time, set the gate voltage of the first semiconductor switch to a low value.
3 . The power conversion circuit of claim 2 , wherein to create the period of operational overlap, the controller is to at a third time between the first time and the second time, set the gate voltage of the second semiconductor switch to a high value.
4 . The power conversion circuit of claim 3 , wherein a duration between the third time and the second time is selected to avoid damage caused by a short-circuit during the period of operation overlap.
5 . The power conversion circuit of claim 1 , wherein the threshold voltage is a minimum amount of charge define by operational characteristics of the first semiconductor switch that is required at the gate to provide the conductive path between the drain and the source.
6 . The power conversion circuit of claim 1 , wherein during the period of operational overlap, a short-circuit occurs between a drain of the first semiconductor switch and ground of the power conversion circuit connected to the source of the second semiconductor switch.
7 . The power conversion circuit of claim 6 , wherein the intermediate value is set to control a surge current during the short-circuit.
8 . The power conversion circuit of claim 1 , wherein the first and second semiconductor switches are metal oxide semiconductor field-effect transistors (MOSFETs) comprising a wide band gap semiconductor material.
9 . The power conversion circuit of claim 8 , wherein the wide band gap semiconductor material is Silicon Carbide (SiC).
10 . The power conversion circuit of claim 1 , including:
a first diode in parallel with a drain and a source of the first semiconductor switch; and
a second diode in parallel with a drain and a source of the second semiconductor switch.
11 . The power conversion circuit of claim 10 , wherein the first and second diode are made of Silicon Carbide (SiC).