Planarization of backside emitting VCSEL and method of manufacturing the same for array application

1. A method of forming a flip chip backside emitting Vertical Cavity Surface Emitting Laser (VCSEL) package comprising:

forming a VCSEL pillar array comprising:

forming a first mirror device on a substrate;

forming an active layer applied directly on the first mirror device generating light;

forming a second mirror device directly attached to the active layer;

applying a metal layer on the second mirror device; and

forming a plurality of pillars, wherein the second mirror device is directly attached to the active layer across an entire width of each pillar, each pillar exposing a portion of the first mirror device, the active region and the second mirror device, wherein each pillar has a diameter between 5-50 μm;

applying a dielectric layer to the VCSEL pillar array, the dielectric layer filling trenches in between VCSEL pillars forming the VCSEL pillar array, covering the VCSEL pillars and the metal layer;

planarizing the VCSEL pillar array to remove the dielectric layer covering the VCSEL pillars exposing the metal layer on a top surface of the VCSEL pillars;

applying a metal coating on the metal layer on the top surface of the VCSEL pillars, the metal layer defining a contact pattern of the VCSEL pillar array, wherein the metal coating attaches a plurality of VCSEL pillars together, and

applying solder on the metal coating to flip chip mount the VCSEL pillar array to a substrate package.

2. The method of claim 1 , comprising forming electrical connections around a perimeter of the VCSEL pillar array connecting a back side of the substrate of the VCSEL array and the substrate package.

3. The method of claim 2 , wherein forming the electrical connections comprises forming is at least one wrap around connection.

4. The method of claim 2 , wherein forming the electrical connections comprises forming at least one conductive via.

5. The method of claim 1 , wherein forming a VCSEL pillar array comprises forming a plurality of pillars by directional Inductive Coupled Plasma-Reactive Ion Etcher (ICP-RIE).

6. The method of claim 1 , wherein the dielectric layer is one of a Polyimide, Benzocyclobutene (BCB) or a solvent based chemical dielectric film.

7. The method of claim 1 , wherein planarizing the VCSEL pillar array to remove the dielectric layer covering the pillars comprises applying a chemical mechanical polishing (CMP) process to the VCSEL array, wherein the metal layer is a CMP index and polish stopper.

8. The method of claim 1 , comprising attaching an optical accessory to a backside of the VCSEL array.