Printed circuit boards with non-functional features
A multi-layer PCB has conductive vias ( 134 ) passing through multiple layers. A layer may have a conductive non-functional feature ( 710 ) physically contacting a via but not surrounding the via, to make the PCB more resistant to thermal stresses while, at the same time, reducing the parasitic capacitance compared to a prior art non-functional pad ( 310 n ).
1. A printed circuit board (PCB) comprising:
a stack of layers each of which comprises an insulator and comprises a portion of a circuitry of the printed circuit board;
two or more holes each of which passes through one or more of the layers; and
two or more conductive vias each of which is formed in a corresponding one of the two or more holes, each via comprising a portion of the circuitry and passing through one or more of the layers;
wherein each of one or more of the layers comprises one or more conductive non-functional features (NFFs), each NFF physically contacting a corresponding via that is one of the two or more vias, wherein an interface between each NFF and the corresponding via does not completely laterally surround the corresponding via;
wherein for at least one said NFF, the corresponding via is one of a pair of differential vias and the corresponding via physically contacts, in the corresponding layer, only the NFF and the insulator, the corresponding layer having only one NFF physically contacting the corresponding via, and the NFF faces away from the other via of the pair.
2. The PCB of claim 1 , wherein each NFF is integral with its corresponding via.
3. The PCB of claim 2 , wherein each NFF comprises over 50 mass % of metal, and the corresponding via comprises over 50 mass % of the same metal.
4. The PCB of claim 1 , wherein for each NFF physically contacting any differential via of the pair, the corresponding via physically contacts, in the corresponding layer, only the NFF and the insulator, and the NFF faces away from the other via of the pair.
5. The PCB of claim 4 , wherein each via in the pair physically contacts at least one NFF.
6. The PCB of claim 4 , wherein each via of the pair physically contacts one or more NFFs facing away from the other via of the pair.
7. The PCB of claim 4 , wherein for at least one NFF physically contacting any differential via of the pair, the corresponding layer includes an NFF physically contacting the other via of the pair.
8. The PCB of claim 4 , wherein for each NFF physically contacting any differential via of the pair, the corresponding layer includes an NFF physically contacting the other via of the pair.
9. The PCB of claim 1 , wherein in top view, at least one NFF forms a ring sector, and the interface between the NFF and the corresponding via is an arc of an inner circle of the ring sector.
10. The PCB of claim 9 , wherein the ring sector spans an angle of at most 150°.
11. The PCB of claim 1 , wherein in top view, for at least one NFF, the corresponding interface has a length of at most 150/360 (150 divided by 360) of a length of the corresponding via's circumference at the corresponding layer.
12. The PCB of claim 11 , wherein the corresponding via physically contacts, in addition to the NFF, only the insulator in the corresponding layer.
13. The PCB of claim 1 , wherein for at least one said NFF, the hole containing the corresponding via passes through the PCB, and the corresponding via passes through a length of the hole but not the entire hole, the hole's diameter being enlarged in the hole's portion beyond the via.
14. The PCB of claim 1 , wherein for said at least one NFF physically contacting one of the vias of the pair, said facing away from the other via of the pair reduces a differential impedance dip caused by the NFF when the pair carries a differential signal.
15. The PCB of claim 14 , wherein the differential signal has a frequency of at least 1 GHz.
16. A printed circuit board (PCB) comprising:
a stack of layers each of which comprises an insulator and comprises a portion of a circuitry of the printed circuit board;
two or more holes each of which passes through one or more of the layers; and
two or more conductive vias each of which is formed in a corresponding one of the two or more holes, each via comprising a portion of the circuitry and passing through one or more of the layers;
wherein each of one or more of the layers comprises one or more conductive non-functional features (NFFs), each NFF physically contacting a corresponding via that is one of the two or more vias, but not completely laterally surrounding the corresponding via;
wherein the conductive vias include a first via and a second via which are operable as differential vias when a differential signal is carried by the first and second vias; and
at least one NFF physically contacts the first via and faces away from the second via to reduce a differential impedance dip caused by the NFF when the differential signal is carried by the first and second vias, the NFF being part of a layer that has only one NFF physically contacting the first via.
17. The PCB of claim 16 , wherein in top view, said at least one NFF protrudes from the first via as a strip running along the first via's circumference and having a uniform width.
18. The PCB of claim 16 , wherein in top view, said at least one NFF is a strip running along the corresponding hole's boundary and having a uniform width.
19. The PCB of claim 16 , wherein each of the first and second vias physically contacts one or more NFFs facing away from the other one of the first and second vias.
20. The PCB of claim 16 , wherein the differential signal has a frequency of at least 1 GHz.