Semiconductor device integrating silicon-based device with semiconductor-based device and method for fabricating the same
A semiconductor device is provided, including a buried oxide layer, having a first side and a second side. A silicon-based device layer is disposed on the first side of the buried oxide layer. The silicon-based device layer includes a first interconnection structure. A semiconductor-based device layer is disposed on the second side of the buried oxide layer. The semiconductor-based device layer includes a second interconnection structure.
1. A semiconductor device, comprising:
a buried oxide layer;
a silicon-based device layer, disposed on the buried oxide layer, wherein the silicon-based device layer comprises a first interconnection structure; and
a semiconductor-based device layer, disposed on the buried oxide layer, wherein the semiconductor-based device layer comprises a second interconnection structure and a GaN layer to provide a channel capability of a semiconductor-based transistor,
wherein the silicon-based device layer and the semiconductor-based device layer are disposed on opposing sides of the buried oxide layer,
wherein the silicon-based device layer includes a MOS transistor,
wherein the semiconductor-based device layer comprises a GaN-based device, and the GaN-based device is a radio frequency (RF) device.
2. The semiconductor device of claim 1 , wherein the silicon-based device layer comprises a silicon layer on the buried oxide layer.
3. The semiconductor device of claim 2 , wherein the buried oxide layer and the silicon layer form a silicon-on-insulator (SOI) structure.
4. The semiconductor device of claim 2 , wherein the buried oxide layer and the GaN layer form a semiconductor-on-insulator structure.
5. The semiconductor device of claim 2 , wherein the GaN-based device is disposed on the GaN layer.
6. The semiconductor device of claim 1 , wherein the buried oxide layer has a thickness to mechanically support the semiconductor-based device layer by direct contact.
7. The semiconductor device of claim 1 ,
wherein the first interconnection structure comprises a first route structure and a first inter-layer dielectric layer enclosing the first route structure,
wherein the second interconnection structure comprises a second route structure and a second inter-layer dielectric layer enclosing the second route structure.
8. The semiconductor device of claim 7 , further comprising a third route structure in the buried oxide layer, to electrically connect the first route structure and the second route structure.
9. The semiconductor device of claim 8 , wherein the third route structure comprises a via through the buried oxide layer to electrically connect the first route structure and the second route structure.