IP Library Granted Patent US 10,680,171
Granted Patent B2
US 10,680,171 · App. 16/262,841 · Granted Jun 9, 2020

Two-terminal reversibly switchable memory device

Inventors: Darrell Rinerson (Cupertino, CA); Christophe J. Chevallier (Palo Alto, CA); Wayne Kinney (Emmett, ID); Roy Lambertson (Los Altos, CA); John E. Sanchez, Jr. (Palo Alto, CA); Lawrence Schloss (Palo Alto, CA); Philip Swab (Santa Rosa, CA); Edmond Ward (Monte Sereno, CA)
Assignee: Hefei Reliance Memory Limited
H01L45/08G06F30/30G11C11/5685G11C13/004G11C13/0007G11C13/0009G11C13/0069H01L27/2436H01L27/2481H01L45/085H01L45/1233H01L45/1246H01L45/1253H01L45/146H01L45/147H01L45/1625G11C2013/005G11C2013/009G11C2013/0045G11C2213/11G11C2213/31G11C2213/32G11C2213/53G11C2213/54G11C2213/56G11C2213/71G11C2213/79
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Quick Facts
Patent No.
US 10,680,171
App. No.
16/262,841
Granted
Jun 9, 2020
Kind
B2
Abstract

A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.

Claims (46)

1. A two-terminal memory cell comprising:

a mixed valence oxide;

a mixed electronic ionic conductor coupled with the mixed valence oxide;

a first memory electrode in contact with the mixed valence oxide; and

a second memory electrode coupled with the mixed electronic ionic conductor.

2. The two-terminal memory cell of claim 1 , wherein:

the mixed electronic ionic conductor is uniform in conduction.

3. The two-terminal memory cell of claim 1 , wherein:

the mixed electronic ionic conductor is lacking in uniformity in conduction.

4. The two-terminal memory cell of claim 3 , wherein:

the uniformity of the mixed electronic ionic conductor varies in a direction from the mixed valence oxide to the second memory electrode.

5. The two-terminal memory cell of claim 3 , wherein:

the uniformity of the mixed electronic ionic conductor varies in a direction orthogonal to a direction from the mixed valence oxide to the second memory electrode.

6. The two-terminal memory cell of claim 1 , wherein:

the mixed valence oxide is uniform in oxidation.

7. The two-terminal memory cell of claim 1 , wherein:

the mixed valence oxide is lacking in uniformity in oxidation.

8. The two-terminal memory cell of claim 7 , wherein:

the uniformity of the mixed valence oxide varies in a direction from the mixed electronic ionic conductor to the first memory electrode.

9. The two-terminal memory cell of claim 8 , wherein:

the uniformity of the mixed valence oxide varies in a direction orthogonal to a direction from the mixed electronic ionic conductor to the first memory electrode.

10. The two-terminal memory cell of claim 1 , wherein the mixed valence oxide is crystalline.

11. A three-terminal memory cell comprising:

a memory element comprising:

a mixed valence oxide, and

a mixed electronic ionic conductor coupled with the mixed valence oxide;

a gate memory electrode coupled with the mixed valence oxide;

a source memory electrode coupled with the memory element; and

a drain memory electrode coupled with the memory element.

12. The three-terminal memory cell of claim 11 , wherein:

the mixed electronic ionic conductor is uniform in conduction.

13. The three-terminal memory cell of claim 11 , wherein:

the mixed electronic ionic conductor is lacking in uniformity in conduction.

14. The three-terminal memory cell of claim 13 , wherein:

the uniformity of the mixed electronic ionic conductor varies in a direction from the mixed valence oxide to at least one of the source memory electrode and the drain memory electrode.

15. The three-terminal memory cell of claim 13 , wherein:

the uniformity of the mixed electronic ionic conductor varies in a direction orthogonal to a direction from the mixed valence oxide to at least one of the source memory electrode and the drain memory electrode.

16. The three-terminal memory cell of claim 11 , wherein:

the mixed valence oxide is uniform in oxidation.

17. The three-terminal memory cell of claim 11 , wherein:

the mixed valence oxide is lacking in uniformity in oxidation.

18. The three-terminal memory cell of claim 17 , wherein:

the uniformity of the mixed valence oxide varies in a direction from the mixed electronic ionic conductor to the gate memory electrode.

19. The three-terminal memory cell of claim 17 , wherein:

the uniformity of the mixed valence oxide varies in a direction orthogonal to a direction from the mixed electronic ionic conductor to the gate memory electrode.

20. The three-terminal memory cell of claim 11 , wherein the mixed valence oxide is crystalline.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2019
From: RINERSON, DARRELL; CHEVALLIER, CHRISTOPHE J.; LAMBERTSON, ROY; KINNEY, WAYNE; SANCHEZ, JOHN E., JR.; SCHLOSS, LAWRENCE; SWAB, PHILIP F.S.; WARD, EDMOND R.
To: UNITY SEMICONDUCTOR CORPORATION
Reel/Frame 048196/0734 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2019
From: UNITY SEMICONDUCTOR CORPORATION
To: HEFEI RELIANCE MEMORY LIMITED
Reel/Frame 048196/0786 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2019
From: RAMBUS INC.
To: HEFEI RELIANCE MEMORY LIMITED
Reel/Frame 048196/0798 →