Debug command execution using existing datapath circuitry

1. An apparatus, comprising:

a processor core that includes:

control circuitry;

path circuitry configured to access data for instructions executed by the processor core;

a plurality of storage elements, wherein the path circuitry is configured to access the storage elements via a port; and

intercept circuitry configured to intercept, between the port and the path circuitry, data accessed from the storage elements and provide the intercepted data to the control circuitry; and

debug circuitry configured to receive external debug inputs and send abstract commands to the processor core based on the external debug inputs;

wherein the control circuitry is configured to, in response to an abstract command to access one or more of the storage elements:

generate an instruction that causes data to be read from one or more of the plurality of storage elements such that the read data proceeds to the path circuitry and the intercept circuitry, wherein the path circuitry is configured to execute the instruction to process the read data and the execution does not change the architectural state of the processor core;

access, via the intercept circuitry, the read data based on the execution of the instruction; and

transmit the accessed read data to the debug circuitry.

2. The apparatus of claim 1 , wherein the one or more storage elements include one or more general purpose registers and the instruction is an OR instruction that specifies a logical OR of logical zeros with the contents of the one or more general purpose registers.

3. The apparatus of claim 1 , wherein the one or more storage elements include one or more control status registers and the instruction is an instruction that transfers a value between the one or more control status registers and one or more other registers.

4. The apparatus of claim 3 , wherein the instruction that transfers the value is a RISC-V csrrs or csrrw instruction.

5. The apparatus of claim 1 , wherein the control circuitry is further configured to:

insert write data from the debug circuitry for storage in the one or more storage elements.

6. The apparatus of claim 1 , wherein the one or more storage elements include memory and the control circuitry is further configured to issue a direct memory access (DMA) command to DMA circuitry of the apparatus based on an abstract command.

7. The apparatus of claim 6 , wherein the control circuitry is further configured to send a request to the DMA circuitry to stop accepting requests and to wait to send the DMA command until the DMA circuitry sends a ready signal.

8. A method, comprising:

receiving, by debug circuitry of a processor, external debug inputs;

sending, by the debug circuitry, abstract commands to a processor core based on the external debug inputs, wherein the processor core includes:

control circuitry;

a plurality of storage elements,

path circuitry that accesses data for instructions executed by the processor core, including accessing the storage elements via one or more ports; and

intercept circuitry that intercepts, between the port and the path circuitry, data accessed from the storage elements and provides the intercepted data to the control circuitry;

generating, by the control circuitry in response to an abstract command to access one or more of the storage elements, an instruction that causes data to be read from one or more of the plurality of storage elements such that the read data proceeds to the path circuitry and the intercept circuitry;

executing, by the path circuitry, the instruction to process the read data, wherein the executing does not change the architectural state of the processor core;

accessing, by the control circuitry via the intercept circuitry, the read data based the execution of the instruction; and

transmitting the accessed read data to the debug circuitry.

9. The method of claim 8 , wherein the instruction is an OR instruction that specifies a logical OR of logical zeros with the contents of one or more general purpose registers.

10. The method of claim 8 , wherein the instruction transfers a value between one or more control status registers and one or more other registers.

11. The method of claim 8 , further comprising:

inserting write data from the debug circuitry for storage in the one or more storage elements.

12. A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, including:

a processor core that includes:

control circuitry;

path circuitry configured to access data for instructions executed by the processor core;

a plurality of storage elements, wherein the path circuitry is configured to access the storage elements via a port; and

intercept circuitry configured to intercept, between the port and the path circuitry, data accessed from the storage elements and provide the intercepted data to the control circuitry; and

debug circuitry configured to receive external debug inputs and send abstract commands to the processor core based on the external debug inputs;

wherein the control circuitry is configured to, in response to an abstract command to access one or more of the storage elements:

generate an instruction that causes data to be read from one or more of the plurality of storage elements such that the read data proceeds to the path circuitry and the intercept circuitry, wherein the path circuitry is configured to execute the instruction to process the read data and the execution does not change the architectural state of the processor core;

access, via the intercept circuitry, the read data based on the execution of the instruction; and

transmit the accessed read data to the debug circuitry.

13. The non-transitory computer readable storage medium of claim 12 , wherein the one or more storage elements include one or more general purpose registers and the instruction is an OR instruction that specifies a logical OR of logical zeros with the contents of the one or more general purpose registers.

14. The non-transitory computer readable storage medium of claim 12 , wherein the one or more storage elements include one or more control status registers and the instruction transfers a value between the one or more control status registers and one or more other registers.

15. The non-transitory computer readable storage medium of claim 12 , wherein the control circuitry is further configured to:

insert write data from the debug circuitry for storage in the one or more storage elements.