Display device having reduced interference

1. A method for reducing electromagnetic interference of a display device, the method comprising:

driving a first gate electrode of a plurality of gate electrodes of the display device with a first gate select signal to select first subpixels of a plurality of subpixels for updating during a first period;

driving a first common electrode of a plurality of common electrodes with a reference signal during the first period, wherein the first common electrode is proximate the first gate electrode;

driving a second common electrode of the plurality of common electrodes with a first interference reduction signal during the first period, the first interference reduction signal comprising a polarity opposite a polarity of the first gate select signal;

driving a selection circuitry control trace with a control signal during a second period; and

driving a first interference reduction trace with a second interference reduction signal during the second period, wherein a polarity of the second interference reduction signal differs from a polarity of the control signal.

2. The method of claim 1 , wherein a peak-to-peak amplitude of the first gate select signal differs from a peak-to-peak amplitude of the first interference reduction signal.

3. The method of claim 1 , wherein one or more of a rise time and a fall time of the first gate select signal differs from one or more of a first time and fall time of the first interference reduction signal.

4. The method of claim 1 , wherein the first interference reduction signal is delayed relative to the first gate select signal.

5. The method of claim 1 further comprising:

driving a second gate electrode of the plurality of gate electrodes with a second gate select signal to select second subpixels of the plurality of subpixels for updating during a third period;

driving a third common electrode of the plurality of common electrodes with the reference signal during the second period, wherein the third common electrode is proximate the second gate electrode; and

driving a fourth common electrode of the plurality of common electrodes with a third interference reduction signal during the third period, the third interference reduction signal comprising a polarity opposite a polarity of the second gate select signal.

6. The method of claim 5 , wherein the first common electrode is driven with the reference signal during the third period and the second common electrode is driven with one of the first interference reduction signal and the reference signal during the third period.

7. The method of claim 6 , wherein at least one of the first interference reduction signal is delayed relative to the third interference reduction signal, a peak-to-peak amplitude of the first interference reduction signal differs from a peak-to-peak amplitude of the third interference reduction signal, and a shape of the of the first interference reduction signal differs from a shape of the third interference reduction signal.

8. A method for reducing electromagnetic interference of a display device, the method comprising:

driving a first gate electrode of a plurality of gate electrodes of the display device with a first gate select signal to select first subpixels of a plurality of subpixels for updating during a first period;

driving a first common electrode of a plurality of common electrodes with a reference signal during the first period, wherein the first common electrode is proximate the first gate electrode;

driving a second common electrode of the plurality of common electrodes with a first interference reduction signal during the first period, the first interference reduction signal comprising a polarity opposite a polarity of the first gate select signal;

driving a multiplexer control trace with a selection signal during a second period; and

driving an interference reduction trace with a second interference reduction signal during the second period, wherein a polarity of the second interference reduction signal differs from a polarity of the selection signal.

9. A display device comprising:

a plurality of gate electrodes;

a plurality of common electrodes;

a plurality of subpixels coupled to the plurality of gate electrodes;

selection circuitry configured to:

drive a first gate electrode of the plurality of gate electrodes with a first gate select signal to select first subpixels of the plurality of subpixels for updating during a first period;

a selection circuitry control trace coupled to the selection circuitry;

a first interference reduction trace; and

a display driver coupled to the selection circuitry control trace and configured to:

drive a first common electrode of the plurality of common electrodes with a reference signal during the first period, wherein the first common electrode is proximate the first gate electrode;

drive a second common electrode of the plurality of common electrodes with a first interference reduction signal during the first period, the first interference reduction signal comprising a polarity opposite a polarity of the first gate select signal;

drive the selection circuitry control trace with a control signal during a second period; and

drive the first interference reduction trace with a second interference reduction signal during the second period, wherein a polarity of the second interference reduction signal differs from a polarity of the control signal.

10. The display device of claim 9 , wherein a peak-to-peak amplitude of the first gate select signal differs from a peak-to-peak amplitude of the first interference reduction signal.

11. The display device of claim 9 , wherein at least one of a rise time and a fall time of the first gate select signal differs from at least one of a first time and fall time of the first interference reduction signal.

12. The display device of claim 9 , wherein the first interference reduction signal is delayed relative to the first gate select signal.

13. A display device comprising:

a plurality of gate electrodes;

a plurality of common electrodes;

a plurality of subpixels coupled to the plurality of gate electrodes;

selection circuitry configured to:

drive a first gate electrode of the plurality of gate electrodes with a first gate select signal to select first subpixels of the plurality of subpixels for updating during a first period;

a plurality of source electrodes;

a multiplexer coupled to the plurality of source electrodes;

a multiplexer control trace coupled to the multiplexer; and

a second first interference reduction trace; and

a display driver configured to:

drive a first common electrode of the plurality of common electrodes with a reference signal during the first period, wherein the first common electrode is proximate the first gate electrode;

drive a second common electrode of the plurality of common electrodes with a first interference reduction signal during the first period, the first interference reduction signal comprising a polarity opposite a polarity of the first gate select signal;

drive the multiplexer control trace with a selection signal during a second period; and

drive the first interference reduction trace with a second interference reduction signal during the second period, wherein a polarity of the second interference reduction signal differs from a polarity of the selection signal.

14. A display driver for a display device, the display driver comprising:

control circuitry configured to output a control signal to instruct selection circuitry to drive a first gate electrode of a plurality of gate electrodes of the display device with a first gate select signal to select first subpixels of the display device for updating during a first period; and

display driver circuitry configured to:

drive a first common electrode of a plurality of common electrodes of the display device with a reference signal during the first period, wherein the first common electrode is proximate the first gate electrode;

drive a second common electrode of the plurality of common electrodes with a first interference reduction signal during the first period, the first interference reduction signal comprising a polarity opposite a polarity of the first gate select signal;

drive a selection signal on a multiplexer control trace during a second period to control a multiplexer; and

drive a second interference reduction signal on a first interference reduction trace during the second period.

15. The display driver of claim 14 , wherein a peak-to-peak amplitude of the first gate select signal differs from a peak-to-peak amplitude of the first interference reduction signal.

16. The display driver of claim 14 , wherein at least one of the first interference reduction signal is delayed relative to the first gate select signal and at least one of a rise time and a fall time of the first gate select signal differs from at least one of a first time and fall time of the first interference reduction signal.

17. The display driver of claim 14 , wherein outputting the control signal to instruct the selection circuitry comprises driving the control signal onto a selection circuitry control trace, and wherein the control circuitry is further configured to drive a third interference reduction signal on second interference reduction trace.