IP Library Granted Patent US 10,860,420
Granted Patent B2
US 10,860,420 · App. 16/268,401 · Granted Dec 8, 2020

Method and system for mitigating read disturb impact on persistent memory

Inventor: Shu Li (Bothell, WA)
Assignee: Alibaba Group Holding Limited
G06F11/1068G11C7/02G11C29/52H03M13/154H03M13/2906
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Quick Facts
Patent No.
US 10,860,420
App. No.
16/268,401
Granted
Dec 8, 2020
Kind
B2
Abstract

One embodiment facilitates data placement in a storage device. During operation, the system receives chunks of data to be written to a non-volatile memory. The system encodes a first chunk based on a first error-correcting code (ECC) to obtain a first ECC-encoded codeword. The system encodes a first group of ECC-encoded codewords which include the first ECC-encoded codeword, based on an erasure code (EC) to obtain a first EC-encoded group, wherein a respective EC-encoded group includes EC parity bits. The system encodes the EC parity bits of the obtained first EC-encoded group based on a second error-correcting code (ECC) to obtain ECC-encoded EC parity bits. The system writes the first EC-encoded group and the ECC-encoded EC parity bits to the non-volatile memory.

Claims (86)

1. A computer-implemented method for facilitating data placement, the method comprising:

receiving chunks of data to be written to a non-volatile memory;

encoding a first chunk based on a first error-correcting code (ECC) to obtain a first ECC-encoded codeword;

encoding a first group of ECC-encoded codewords which include the first ECC-encoded codeword, based on an erasure code (EC) to obtain a first EC-encoded group, wherein a respective EC-encoded group includes EC parity bits; and

writing the first EC-encoded group to the non-volatile memory.

2. The method of claim 1 , further comprising:

encoding the EC parity bits of the obtained first EC-encoded group based on a second error-correcting code (ECC) to obtain ECC-encoded parity bits,

wherein writing the first EC-encoded group to the non-volatile memory further comprises writing the ECC-encoded EC parity bits to the non-volatile memory,

wherein the first error-correcting code provides a first uncorrectable bit error rate, wherein the second error-correcting code provides a second uncorrectable bit error rate, and wherein the first rate is a predetermined amount greater than the second rate.

3. The method of claim 2 ,

wherein the ECC-encoded codewords of the first group are encoded based on the first error-correcting code, wherein the first ECC-encoded codeword includes short ECC parity bits, wherein the ECC-encoded EC parity bits comprise strong ECC parity bits, and wherein a first error rate associated with the encoding to obtain the short ECC parity bits is greater than a second error rate associated with the encoding to obtain the ECC-encoded EC parity bits.

4. The method of claim 2 , wherein in response to receiving a request to read the first chunk of data, the method further comprises:

reading the first ECC-encoded codeword from the non-volatile memory;

decoding the first ECC-encoded codeword based on the first error-correcting code;

in response to unsuccessfully decoding the first ECC-encoded codeword based on the first error-correcting code, decoding the first EC-encoded group based on the erasure code;

in response to unsuccessfully decoding the first EC-encoded group based on the erasure code, decoding the ECC-encoded EC parity bits based on the second error-correcting code; and

in response to unsuccessfully decoding the ECC-encoded EC parity bits based on the second error-correcting code, generating a failure notification for the host.

5. The method of claim 4 , further comprising:

in response to successfully decoding the first ECC-encoded codeword based on the first error-correcting code, successfully reading the first chunk of data;

in response to successfully decoding the first EC-encoded group based on the erasure code, successfully reading the first chunk of data; and

in response to successfully decoding the ECC-encoded EC parity bits based on the second error-correcting code, decoding the first EC-encoded group based on the erasure code.

6. The method of claim 2 , wherein writing the first EC-encoded group and the ECC-encoded EC parity bits to the non-volatile memory further comprises:

distributing the first EC-encoded group and the ECC-encoded EC parity bits for placement onto a plurality of ranks of physical media of the non-volatile memory.

7. The method of claim 2 , further comprising:

tracking, by an error statistics module, an error count and an error pattern associated with decoding the first EC-encoded group;

in response to detecting a condition to re-map the data stored in the first EC-encoded group, determining a new physical address in the non-volatile memory at which to store the first EC-encoded group; and

writing the first EC-encoded group and the ECC-encoded EC parity bits to the non-volatile memory at the new physical address.

8. The method of claim 7 , wherein the condition to re-map the data is based on one or more of:

a predetermined threshold for the error count or the error pattern;

a predetermined time period or interval;

an access frequency of the data stored in the first EC-encoded group;

a garbage collection process; and

a background operation associated with re-mapping data.

9. The method of claim 2 , wherein the non-volatile memory is coupled to a central processing unit and includes:

an interface for communicating with the central processing unit;

a non-volatile memory controller which performs encoding based on the first error-correcting code, the erasure code, and the second error-correcting code; and

physical media associated with a plurality of ranks of the non-volatile memory to which data is to be written for persistent storage.

10. A computer system for facilitating data placement, the system comprising:

a processor; and

a memory coupled to the processor and storing instructions, which when executed by the processor cause the processor to execute the instructions in a plurality of steps, the steps comprising:

receiving chunks of data to be written to a non-volatile memory;

encoding a first chunk based on a first error-correcting code (ECC) to obtain a first ECC-encoded codeword;

encoding a first group of ECC-encoded codewords which include the first ECC-encoded codeword, based on an erasure code (EC) to obtain a first EC-encoded group, wherein a respective EC-encoded group includes EC parity bits; and

writing the first EC-encoded group to the non-volatile memory.

11. The computer system of claim 10 , wherein the steps further comprise:

encoding the EC parity bits of the obtained first EC-encoded group based on a second error-correcting code (ECC) to obtain ECC-encoded parity bits,

wherein writing the first EC-encoded group to the non-volatile memory further comprises writing the ECC-encoded EC parity bits to the non-volatile memory, wherein the first error-correcting code provides a first uncorrectable bit error rate, wherein the second error-correcting code provides a second uncorrectable bit error rate, and wherein the first rate is a predetermined amount greater than the second rate.

12. The computer system of claim 11 ,

wherein the ECC-encoded codewords of the first group are encoded based on the first error-correcting code, wherein the first ECC-encoded codeword includes short ECC parity bits, wherein the ECC-encoded EC parity bits comprise strong ECC parity bits, and wherein a first error rate associated with the encoding to obtain the short ECC parity bits is greater than a second error rate associated with the encoding to obtain the ECC-encoded EC parity bits.

13. The computer system of claim 11 , wherein in response to receiving a request to read the first chunk of data, the steps further comprise:

reading the first ECC-encoded codeword from the non-volatile memory;

decoding the first ECC-encoded codeword based on the first error-correcting code;

in response to unsuccessfully decoding the first ECC-encoded codeword based on the first error-correcting code, decoding the first EC-encoded group based on the erasure code;

in response to unsuccessfully decoding the first EC-encoded group based on the erasure code, decoding the ECC-encoded EC parity bits based on the second error-correcting code; and

in response to unsuccessfully decoding the ECC-encoded EC parity bits based on the second error-correcting code, generating a failure notification for the host.

14. The computer system of claim 13 , wherein the steps further comprise:

in response to successfully decoding the first ECC-encoded codeword based on the first error-correcting code, successfully reading the first chunk of data;

in response to successfully decoding the first EC-encoded group based on the erasure code, successfully reading the first chunk of data; and

in response to successfully decoding the ECC-encoded EC parity bits based on the second error-correcting code, decoding the first EC-encoded group based on the erasure code.

15. The computer system of claim 11 , wherein writing the first EC-encoded group and the ECC-encoded EC parity bits to the non-volatile memory further comprises:

distributing the first EC-encoded group and the ECC-encoded EC parity bits for placement onto a plurality of ranks of physical media of the non-volatile memory.

16. The computer system of claim 11 , wherein the steps further comprise:

tracking, by an error statistics module, an error count and an error pattern associated with decoding the first EC-encoded group;

in response to detecting a condition to re-map the data stored in the first EC-encoded group, determining a new physical address in the non-volatile memory at which to store the first EC-encoded group; and

writing the first EC-encoded group and the ECC-encoded EC parity bits to the non-volatile memory at the new physical address.

17. The computer system of claim 16 , wherein the condition to re-map the data is based on one or more of:

a predetermined threshold for the error count or the error pattern;

a predetermined time period or interval;

an access frequency of the data stored in the first EC-encoded group;

a garbage collection process; and

a background operation associated with re-mapping data.

18. The computer system of claim 11 , wherein the non-volatile memory is coupled to a central processing unit and includes:

an interface for communicating with the central processing unit;

a non-volatile memory controller which performs encoding based on the first error-correcting code, the erasure code, and the second error-correcting code; and

physical media associated with a plurality of ranks of the non-volatile memory to which data is to be written for persistent storage.

19. A non-transitory computer-readable storage medium storing instructions that when executed by a computer cause the computer to execute the instructions in a plurality of steps, the steps comprising:

receiving chunks of data to be written to a non-volatile memory;

encoding a first chunk based on a first error-correcting code (ECC) to obtain a first ECC-encoded codeword;

encoding a first group of ECC-encoded codewords which include the first ECC-encoded codeword, based on an erasure code (EC) to obtain a first EC-encoded group, wherein a respective EC-encoded group includes EC parity bits; and

writing the first EC-encoded group to the non-volatile memory.

20. The storage medium of claim 19 , wherein in response to receiving a request to read the first chunk of data, the steps further comprise:

reading the first ECC-encoded codeword from the non-volatile memory;

decoding the first ECC-encoded codeword based on the first error-correcting code;

in response to unsuccessfully decoding the first ECC-encoded codeword based on the first error-correcting code, decoding the first EC-encoded group based on the erasure code;

in response to unsuccessfully decoding the first EC-encoded group based on the erasure code, decoding the ECC-encoded EC parity bits based on the second error-correcting code; and

in response to unsuccessfully decoding the ECC-encoded EC parity bits based on the second error-correcting code, generating a failure notification for the host.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2026
From: ALIBABA GROUP HOLDING LIMITED
To: CLOUD INTELLIGENCE ASSETS HOLDING (SINGAPORE) PRIVATE LIMITED
Reel/Frame 075499/0384 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2019
From: LI, SHU
To: ALIBABA GROUP HOLDING LIMITED
Reel/Frame 048253/0516 →
Continuity (1)
Related Publication 20200250031A1 · Aug 6, 2020