High voltage semiconductor device including a doped gate electrode
A high voltage semiconductor device includes a semiconductor region of a first conductivity type having a first region and a second region, a first insulation pattern disposed over the first region of the semiconductor region. A second insulation pattern is disposed over the second region of the semiconductor region. The second insulation pattern has a thickness greater than a thickness of the first insulation pattern. A gate electrode is disposed over the first and second insulation patterns to have a step structure over a boundary region between the first and second regions. The gate electrode has a doping profile such that a position of a maximum projection range of impurity ions distributed in the gate electrode over the first region is located at substantially the same level as a position of a maximum projection range of impurity ions distributed in the gate electrode over the second region. A top surface of the gate electrode over the second region is located at a level higher than a level of a top surface of the gate electrode over the first region.
1. A high voltage semiconductor device comprising:
a semiconductor region of a first conductivity type having a first region and a second region;
a first insulation pattern disposed over the first region of the semiconductor region to have a first thickness;
a second insulation pattern disposed over the second region of the semiconductor region to have a second thickness greater than the first thickness; and
a gate electrode disposed over the first and second insulation patterns to have a step structure over a boundary region between the first and second regions,
wherein the gate electrode has a doping profile such that a position of a maximum projection range of impurity ions distributed in the gate electrode over the first region is located at substantially the same level as a position of a maximum projection range of impurity ions distributed in the gate electrode over the second region, and
wherein a top surface of the gate electrode over the second region is located at a level higher than a level of a top surface of the gate electrode over the first region.
2. The high voltage semiconductor device of claim 1 ,
wherein the first region vertically overlaps with the first insulation pattern and a portion of the gate electrode; and
wherein the second region vertically overlaps with the second insulation pattern and another portion of the gate electrode.
3. The high voltage semiconductor device of claim 1 ,
wherein the first insulation pattern is a gate insulation pattern; and
wherein the second insulation pattern is a field plate insulation pattern.
4. The high voltage semiconductor device of claim 1 ,
wherein a bottom surface of the first insulation pattern is located at substantially the same level as a bottom surface of the second insulation pattern; and
wherein a top surface of the second insulation pattern is located at a level higher than a level of a top surface of the first insulation pattern.
5. The high voltage semiconductor device of claim 1 , wherein each of the first and second insulation patterns includes an oxide layer.
6. The high voltage semiconductor device of claim 1 , wherein a thickness of the gate electrode over the first region is substantially equal to a thickness of the gate electrode over the second region.
7. The high voltage semiconductor device of claim 1 , wherein a level difference between a top surface of the gate electrode over the first region and a top surface of the gate electrode over the second region is substantially equal to a level difference between a top surface of the first insulation pattern over the first region and a top surface of the second insulation pattern over the second region.
8. The high voltage semiconductor device of claim 1 , further comprising:
a body region of the first conductivity type disposed in an upper portion of the semiconductor region;
a source region of a second conductivity type disposed in an upper portion of the body region of the first conductivity type; and
a drain region of the second conductivity type disposed in an upper portion of the semiconductor region.
9. The high voltage semiconductor device of claim 8 , wherein the second insulation pattern over the second region extends onto a portion of the drain region.
10. A semiconductor device comprising:
a gate electrode disposed over first and second insulation patterns to have a step structure on a boundary region between the first and second insulation patterns,
wherein the gate electrode has a doping profile such that a position of a maximum projection range of impurity ions distributed in the gate electrode over the first insulation pattern is located at substantially the same level as a position of a maximum projection range of impurity ions distributed in the gate electrode over the second insulation pattern, and
wherein a top surface of the gate electrode over the second insulation pattern is located at a level higher than a level of a top surface of the gate electrode over the first insulation pattern.