IP Library Granted Patent US 10,530,483
Granted Patent B2
US 10,530,483 · App. 16/268,702 · Granted Jan 7, 2020

Systems and methods for biasing optical modulating devices

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Quick Facts
Patent No.
US 10,530,483
App. No.
16/268,702
Granted
Jan 7, 2020
Kind
B2
Abstract

Systems and methods described herein include methods and systems for controlling bias voltage provided to an optical modulating device. The optical modulating device is biased at a bias point that is different from a null point of the device such that an offset to the received optical power due to limited extinction ratio is reduced.

Claims (34)

1. An apparatus comprising:

a first optical modulating element having a first null point corresponding to a first level of a first bias signal;

a second optical modulating element having a second null point corresponding to a second level of a second bias signal; and

a bias controller configured to,

adjust the first bias signal according to a first error signal responsive to a first dither signal applied to the first bias signal from the first level to a first target level that biases the first modulating element at a first target bias point different from the first null point, and

adjust the second bias signal according to a second error signal responsive to a second dither signal applied to the second bias signal from the second level to a second target level that biases the second modulating element at a second target bias point different from the second null point,

wherein the adjustment of the first bias signal and the adjustment of the second bias signal reduce electric field coupling between the first modulating element and the second modulating element.

2. An apparatus as in claim 1 further comprising an optical receiver.

3. An apparatus as in claim 1 implemented in a router.

4. An apparatus as in claim 1 implemented in a server.

5. An apparatus as in claim 1 implemented in a switch.

6. An apparatus as in claim 1 further comprising a data driver configured to:

provide a first data signal to the first modulating element; and

provide a second data signal to the second modulating element.

7. An apparatus as in claim 6 wherein:

the first modulating element is configured to generate the first modulated optical signal based on modulating the light beam with the first data signal; and

the second modulating element is configured to generate the second modulated optical signal based on based on modulating the light beam with the second data signal.

8. An apparatus as in claim 6 further comprising a transceiver that includes the data driver.

9. An apparatus as in claim 6 wherein the first data signal and the second data signal are encoded in a phase-shift keying format.

10. An apparatus as in claim 6 wherein the first data signal and the second data signal are encoded in a pulse-amplitude modulation format.

11. An apparatus as in claim 1 wherein:

the first error signal corresponds to the response of the first modulating element to the first dither signal; and

the second error signal corresponds to the response of the second modulating element to the second dither signal.

12. An apparatus as in claim 1 wherein the bias controller is configured to:

adjust the first bias signal by an amount proportional to the first error signal; and

adjust the second bias signal by an amount proportional to the second error signal.

13. An apparatus as in claim 1 wherein the bias controller comprises a first digital-to-analog converter (DAC).

14. An apparatus as in claim 1 wherein:

the bias controller further comprises a second digital-to-analog converter (DAC) configured to generate the second bias signal; and

the first DAC is configured to generate the first bias signal.

15. An apparatus as in claim 1 wherein the first modulating element comprises a Mach-Zehnder Modulator (MZM).

16. An apparatus as in claim 1 wherein the first modulating element has a non-linear transfer function.

17. An apparatus as in claim 1 wherein the bias controller comprises a digital signal processor (DSP), an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA).

18. An apparatus as in claim 1 wherein the bias controller includes a feedback loop.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE LTD.
Reel/Frame 057336/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: MARVELL TECHNOLOGY CAYMAN I
To: CAVIUM INTERNATIONAL
Reel/Frame 057279/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: INPHI CORPORATION
To: MARVELL TECHNOLOGY CAYMAN I
Reel/Frame 056649/0823 →