Suppression of program disturb with bit line and select gate voltage regulation
Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.
1. A method for suppression of program disturb, the method comprising:
programming a first memory cell in a flash memory array that comprises rows and columns of memory cells, wherein the memory cells in a particular row are coupled to a particular source line and to a particular select-gate (SG) line, and wherein the memory cells in a particular column are coupled to a particular bit line;
regulating a first voltage of a selected SG line coupled to the first memory cell independently of a power supply voltage of the flash memory array during the programming of the first memory cell; and
regulating a second voltage of an unselected bit line coupled to a second memory cell of the flash memory array independently of the power supply voltage during the programming of the first memory cell, wherein the second memory cell is adjacent to the first memory cell in the same row of the flash memory array;
wherein, during the programming of the first memory cell, the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.
2. The method of claim 1 , wherein regulating the first voltage comprises operating the first voltage lower than the power supply voltage.
3. The method of claim 1 , wherein regulating the second voltage comprises operating the second voltage higher than the power supply voltage.
4. The method of claim 1 , further comprising adjusting at least one of the first voltage and the second voltage based on an operating temperature of the flash memory array.
5. The method of claim 4 , wherein adjusting at least one of the first voltage and the second voltage comprises sensing the operating temperature of the flash memory array.
6. The method of claim 1 , wherein trim values for the first voltage and the second voltage are configured for each block of memory cells in the flash memory array.
7. The method of claim 1 , wherein trim values for the first voltage and the second voltage are configured at the time of manufacture of a non-volatile memory (NVM) device that comprises the flash memory array.
8. The method of claim 1 , wherein the memory cells of the flash memory array are spilt-gate memory cells manufactured as 40 nm nodes.
9. The method of claim 1 , wherein the memory cells of the flash memory array are two-transistor (2T) memory cells manufactured as 40 nm nodes.
10. The method claim 1 , wherein the flash memory array is embedded in a non-volatile memory (NVM) device.