Configurable sensing systems and methods for configuration
A sensor system can include a sensor configured to output raw sensor data, a plurality of processing modules configured to process the raw sensor data from the sensor to output processed sensor data, a state module for each processing module operative to cause a respective processing module to receive and/or process the sensor data, and a control module configured to receive a bitmask and to operate each state module based on the bitmask to control which processing modules process the sensor data and/or an order of processing. The bitmask can include a plurality of discrete bits. Each state module and/or processing module can be associated with at least one discrete bit.
1. A sensor system, comprising:
a sensor configured to output raw sensor data;
a plurality of processing modules configured to process the raw sensor data from the sensor to output processed sensor data;
a plurality of state modules, at least one state module for each processing module operative to cause a respective processing module to receive and/or process the sensor data; and
a control module configured to receive a bitmask and to operate each state module based on the bitmask to control which processing modules process the sensor data and/or an order of processing, wherein each state module is directly connected to an input of the respective processing module and directly connected to an input of a respective OR block, wherein an output of the respective processing module is connected to the input of the logic gate, wherein the state module is configured to either output to the respective processing module or the logic gate to bypass the respective processing module, wherein the respective logic gate is configured to output only data from one of a respective state module or a respective processing module.
2. The system of claim 1 , wherein the bitmask includes a plurality of discrete bits, wherein each state module and/or processing module is associated with at least one discrete bit.
3. The system of claim 2 , wherein each discrete bit is configured to include 1 or 0.
4. The system of claim 3 , wherein each state module is configured to be turned on when an associated bit is a 1, and wherein each state module is configured to be turned off when an associated bit is a 0.
5. The system of claim 1 , wherein the state module is operative to configure one or more processing characteristics of the respective processing module.
6. The system of claim 1 , further including a first state module configured to receive raw sensor data from the sensor or a first logic gate connected to the sensor.
7. The system of claim 6 , further including a last state module or last logic gate configured to output processed data from the sensor system.
8. The system of claim 7 , wherein each state module after the first state module is connected to the respective logic gate to receive input from the respective logic gate.
9. The system of claim 1 , wherein the sensor is a data probe for an aircraft.
10. The system of claim 1 , wherein the data probe includes an accelerometer.
11. A signal processing system, comprising;
a plurality of processing modules configured to process raw sensor data from a sensor to output processed sensor data;
a plurality of state modules, at least one for each processing module operative to cause a respective processing module to receive and/or process the sensor data; and
a control module configured to receive a bitmask and to operate each state module based on the bitmask to control which processing modules process the sensor data and/or an order of processing, wherein each state module is directly connected to an input of the respective processing module and directly connected to an input of a respective OR block, wherein an output of the respective processing module is connected to the input of the logic gate, wherein the state module is configured to either output to the respective processing module or the logic gate to bypass the respective processing module, wherein the respective logic gate is configured to output only data from one of a respective state module or a respective processing module.
12. The system of claim 11 , wherein the bitmask includes a plurality of discrete bits, wherein each state module and/or processing module is associated with at least one discrete bit.
13. The system of claim 12 , wherein each discrete bit is configured to include 1 or 0.
14. The system of claim 13 , wherein each state module is configured to be turned on when an associated bit is 1, and wherein each state module is configured to be turned off when an associated bit is 0.
15. The system of claim 11 , wherein the state module is operative to configure one or more processing characteristics of a respective processing module.
16. The system of claim 11 , wherein each state module is connected to an input of the respective processing module and an input of a respective logic gate, wherein an output of the respective processing module is connected to the input of the logic gate, wherein the state module is configured to either output to the respective processing module or the logic gate to bypass the respective processing module, wherein the respective logic gate is configured to output only data from one of a respective state module or a respective processing module.
17. The system of claim 16 , further including a first state module configured to receive raw sensor data from the sensor or a first logic gate connected to the sensor.
18. A method for signal processing, comprising:
creating a bitmask having discrete bits, each discrete bit associated with a respective processing module; and
sending the bitmask to a control module to control which processing modules process sensor data and/or in which order;
operating a state module that is directly connected to each processing module and to a respective logic block to select processing modules and/or an order thereof to process sensor data using the control module based on the bitmask; and
processing sensor data using the processing modules in accordance with the bitmask to output processed data.
19. The method of claim 18 , wherein creating the bitmask comprises assigning a 1 or a 0 to each discrete bit, wherein selecting processing modules includes using the respective processing module when an associated bit is 1, and not using a respective processing module when an associated bit is 0.