System and method of rerouting an inter-processor communication link based on a link utilization value
In one or more embodiments, one or more systems, methods, and/or processes may configure multiple link registers, of a first semiconductor package of an information handling system (IHS), that configure an input/output (I/O) communication fabric of the first semiconductor package to route communications of multiple components of the first semiconductor package to multiple inter-processor communication link interfaces; may communicate with a second semiconductor package of the IHS via the multiple inter-processor communication link interfaces; may determine that a link utilization value of multiple link utilization values is at or above a threshold value; and may configure a link register of the multiple link registers, associated with the at least one component of the multiple components, that configures the I/O communication fabric to route communications of the at least one component of the multiple components to a second inter-processor communication link interface of the multiple inter-processor communication link interfaces.
1. An information handling system, comprising:
a plurality of semiconductor packages, each of the plurality of packages includes a plurality of processor cores and an input/output (I/O) communication fabric; and
a memory medium, coupled to a processor core of a first semiconductor package of the plurality of semiconductor packages, that stores instructions executable by the processor core of the first semiconductor package, which when executed by the processor core of the first semiconductor package, cause the information handling system to:
configure a plurality of link registers, of the first semiconductor package, that configure the I/O communication fabric of the first semiconductor package to route communications of a plurality of components of the first semiconductor package to a plurality of inter-processor communication link interfaces of the first semiconductor package;
wherein the first semiconductor package is configured to:
communicate with a second semiconductor package of the plurality of semiconductor packages via the plurality of inter-processor communication link interfaces;
determine a plurality of link utilization values respectively associated with the plurality of inter-processor communication link interfaces;
store the plurality of link utilization values via a respective plurality of link utilization registers;
retrieve the plurality of link utilization values from the respective plurality of link utilization registers;
monitor the plurality of link utilization values via the respective plurality of link utilization registers;
determine that a link utilization value of the plurality of link utilization values is at or above a threshold value;
in response to determining that the link utilization value of the plurality of link utilization values is at or above the threshold value, generate an interrupt request (IRQ);
provide the IRQ to the processor core of the first semiconductor package;
wherein the processor core of the first semiconductor package is configured to:
receive the IRQ;
wherein the instructions further cause the information handling system to:
determine that communications of at least one component of the plurality of components are routed, by the I/O communication fabric, to a first inter-processor communication link interface of the plurality of inter-processor communication link interfaces; and
in response to the processor core of the first semiconductor package receiving the IRQ, configure a link register of the plurality of link registers, associated with the at least one component of the plurality of components, that configures the I/O communication fabric to route communications of the at least one component of the plurality of components to a second inter-processor communication link interface of the plurality of inter-processor communication link interfaces.
2. The information handling system of claim 1 , wherein the at least one component of the plurality of components includes the processor core of the first semiconductor package.
3. The information handling system of claim 1 , wherein the at least one component of the plurality of components includes at least one I/O module.
4. The information handling system of claim 1 , wherein, to configure the plurality of link registers, of the first semiconductor package, that configure the I/O communication fabric of the first semiconductor package to route communications of the plurality of components of the first semiconductor package to the plurality of inter-processor communication link interfaces of the first semiconductor package, the instructions further cause the information handling system to:
configure a link register of the plurality of link registers associated with a first component of the plurality of components to utilize a first inter-processor communication link interface of the plurality of inter-processor communication link interfaces; and
configure respective link registers associated with other components, other than the first component, of the plurality of components to utilize other inter-processor communication link interfaces, other than the first inter-processor communication link interface, of the plurality of inter-processor communication link interfaces.
5. The information handling system of claim 1 ,
wherein the first semiconductor package includes a comparator; and
wherein, to determine that the link utilization value of the plurality of link utilization values is at or above the threshold value, the comparator is configured to compare the link utilization value with the threshold value.
6. The information handling system of claim 1 , wherein the plurality of processor cores includes at least one graphics processing unit.
7. The information handling system of claim 1 , wherein at least one of the plurality of inter-processor communication link interfaces includes a plurality of serializers/deserializers.
8. The information handling system of claim 3 , wherein the at least one I/O module includes at least one peripheral component interconnect express (PCIe) root complex.
9. The information handling system of claim 4 , wherein the first component of the plurality of components includes a processor core of the plurality of processor cores.
10. A method, comprising:
configuring a plurality of link registers, of a first semiconductor package of an information handling system, that configure an input/output (I/O) communication fabric of the first semiconductor package to route communications of a plurality of components of the first semiconductor package to a plurality of inter-processor communication link interfaces of the first semiconductor package;
the first semiconductor package communicating with a second semiconductor package of the information handling system via the plurality of inter-processor communication link interfaces;
determining a plurality of link utilization values respectively associated with the plurality of inter-processor communication link interfaces;
storing the plurality of link utilization values via a respective plurality of link utilization registers;
retrieving the plurality of link utilization values from the respective plurality of link utilization registers;
monitoring the plurality of link utilization values via the respective plurality of link utilization registers;
determining that a link utilization value of the plurality of link utilization values is at or above a threshold value;
in response to the determining that the link utilization value of the plurality of link utilization values is at or above the threshold value, generating an interrupt request (IRQ);
providing the IRQ to a processor of the first semiconductor package;
the processor of the first semiconductor package receiving the IRQ; and
in response to the processor of the first semiconductor package receiving the IRQ, the processor of the first semiconductor package:
determining that communications of at least one component of the plurality of components are routed, by the I/O communication fabric, to a first inter-processor communication link interface of the plurality of inter-processor communication link interfaces; and
configuring a link register of the plurality of link registers, associated with the at least one component of the plurality of components, that configures the I/O communication fabric to route communications of the at least one component of the plurality of components to a second inter-processor communication link interface of the plurality of inter-processor communication link interfaces.
11. The method of claim 10 , wherein the at least one component of the plurality of components includes the processor.
12. The method of claim 10 , wherein the at least one component of the plurality of components includes at least one I/O module.
13. The method of claim 10 , wherein the configuring the plurality of link registers, of the first semiconductor package of an information handling system, that configure the I/O communication fabric of the first semiconductor package to route communications of the plurality of components of the first semiconductor package to the plurality of inter-processor communication link interfaces of the first semiconductor package includes:
configuring a link register of the plurality of link registers associated with a first component of the plurality of components to utilize a first inter-processor communication link interface of the plurality of inter-processor communication link interfaces; and
configuring respective link registers associated with other components, other than the first component, of the plurality of components to utilize other inter-processor communication link interfaces, other than the first inter-processor communication link interface, of the plurality of inter-processor communication link interfaces.
14. The method of claim 10 , wherein the determining that the link utilization value of the plurality of link utilization values is at or above the threshold value includes a comparator comparing the link utilization value with the threshold value.
15. The method of claim 10 , wherein at least one of the plurality of inter-processor communication link interfaces includes a plurality of serializers/deserializers.
16. The method of claim 10 , wherein the plurality of components of the first semiconductor package includes at least one graphics processing unit.
17. The method of claim 12 , wherein the at least one I/O module includes at least one peripheral component interconnect express (PCIe) root complex.
18. The method of claim 13 , wherein the first component of the plurality of components includes a processor core.