IP Library Granted Patent US 10,965,347
Granted Patent B2
US 10,965,347 · App. 16/271,740 · Granted Mar 30, 2021

Tightly-coupled near-field communication-link connector-replacement chips

Inventor: Gary D. McCormack (Tigard, OR)
Assignee: Keyssa, Inc.
H04B5/02
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Quick Facts
Patent No.
US 10,965,347
App. No.
16/271,740
Granted
Mar 30, 2021
Kind
B2
Abstract

Tightly-coupled near-field transmitter/receiver pairs are deployed such that the transmitter is disposed at a terminal portion of a first conduction path, the receiver is disposed at a terminal portion of a second conduction path, the transmitter and receiver are disposed in close proximity to each other, and the first conduction path and the second conduction path are discontiguous with respect to each other. In some embodiments of the present invention, close proximity refers to the transmitter antenna and the receiver antenna being spaced apart by a distance such that, at wavelengths of the transmitter carrier frequency, near-field coupling is obtained. In some embodiments, the transmitter and receiver are disposed on separate substrates that are moveable relative to each other. In alternative embodiments, the transmitter and receiver are disposed on the same substrate.

Claims (31)

1. A system comprising:

a first substrate defining a first plane;

a first communication chip disposed on the first substrate and comprising:

a plurality of input terminals comprising at least a first input terminal and a second input terminal,

a data aggregation circuit configured to receive a first signal from the first input terminal and a second signal from the second input terminal, and configured to combine the first and second signals to generate an aggregated signal, and

a first near-field transmitter configured to receive the aggregated signal from the data aggregation circuit and to transmit the aggregated signal at a first transmit carrier frequency in the extremely high frequency (EHF) range;

a second communication chip disposed on the first substrate, the second communication chip adjacent to the first communication chip and comprising a first near-field receiver configured to receive a transmitted signal at the first carrier frequency from a second near-field transmitter different from the first near-field transmitter;

a second substrate defining a second plane; and

a third communication chip disposed on the second substrate and comprising:

a second near-field receiver operable to near-field couple with the first near-field transmitter at the first transmit carrier frequency and to receive the aggregated signal, and

a data de-aggregation circuit configured to receive the aggregated signal from the receiver and to extract the first signal and the second signal from the aggregated signal,

wherein the first substrate and the second substrate are positioned such that the first and second planes are not co-planar, and wherein the first near-field transmitter and the second near-field receiver are disposed within a near-field coupling distance of each other at the first transmitter carrier frequency.

2. The system of claim 1 , wherein the aggregated signal is a modulated carrier signal generated by modulating the first and second signals at the first carrier frequency, and wherein the data de-aggregation circuit is configured to demodulate the aggregated signal to obtain the first signal and the second signal.

3. The system of claim 1 , wherein the data aggregation circuit comprises a serializer circuit configured to serialize the first signal and the second signal.

4. The system of claim 1 , wherein the data de-aggregation circuit comprises a deserializer circuit configured to deserialize the first and second signals from the aggregated signal.

5. The system of claim 1 , wherein the data de-aggregation circuit is configured to couple the extracted first signal to a first output terminal of the third communication chip, and to couple the extracted second signal to a second output terminal of the third communication chip.

6. The system of claim 1 , wherein the first substrate on which the first communication chip is disposed corresponds to an electronic device, and wherein the second substrate on which the third communication chip is disposed corresponds to a backplane.

7. The system of claim 6 , wherein the first communication chip is at an edge of the electronic device that is adjacent to the backplane.

8. The system of claim 6 , wherein the electronic device is aligned to the backplane by a rack.

9. The system of claim 1 , wherein the first substrate corresponds to an electronic device, and the first communication ship is spaced inwardly from a peripheral edge of the electronic device by a predetermined amount.

10. The system of claim 1 , wherein the first communication chip is spaced 2 mm to 5 mm from the third communication chip.

11. The system of claim 1 , wherein the first substrate and the second substrate are positioned such that the first plane is oriented at 90 degrees relative to the second plane.

12. The system of claim 1 :

wherein the first communication chip is a first transceiver chip comprising the transmitter and an additional receiver coupled to a first antenna, and

wherein the third communication chip is a second transceiver chip comprising the receiver and an additional transmitter coupled to a second antenna.

13. The system of claim 1 , wherein at least one of the first input terminal and the second input terminal is configured to receive the first signal or the second signal as a differential signal.

14. The system of claim 1 , further comprising:

a fourth communication chip disposed on the second substrate, the fourth communication chip comprising a second near-field transmitter configured to transmit a second signal at the first transmit carrier frequency;

a third substrate; and

a fifth communication chip disposed on the third substrate, the fifth communication chip comprising a third near-field receiver operable to near-field couple with the second near-field transmitter at the first transmit carrier frequency to receive the second signal.

15. The system of claim 1 , wherein the first communication chip is spaced inwardly from a peripheral edge of the first substrate by a first amount.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2022
From: KEYSSA, INC.
To: KEYSSA (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
Reel/Frame 061521/0271 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2022
From: KEYSSA (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
To: MOLEX, LLC
Reel/Frame 061521/0305 →
CHANGE OF NAME Recorded Sep 24, 2019
From: WAVECONNEX, INC.
To: KEYSSA, INC.
Reel/Frame 052159/0122 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2019
From: MCCORMACK, GARY DAVIS
To: WAVECONNEX, INC.
Reel/Frame 049931/0199 →
Continuity (5)
Continuation 15679125 · Aug 16, 2017
Continuation 14047924 · Oct 7, 2013
Continuation 12655041 · Dec 21, 2009
Provisional Application 61203702 · Dec 23, 2008
Related Publication 20190379426A1 · Dec 12, 2019