IP Library Granted Patent US 10,862,466
Granted Patent B2
US 10,862,466 · App. 16/271,824 · Granted Dec 8, 2020

Dynamic time constant for quick decision level acquisition

Inventors: Miguel Valencia (Bristol, GB); Nikolaos Vogiatzis (Bristol, GB)
Assignee: Semtech Corporation
H03K5/003H04B10/25H04B10/27
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Quick Facts
Patent No.
US 10,862,466
App. No.
16/271,824
Granted
Dec 8, 2020
Kind
B2
Abstract

A circuit controls a dynamic time constant to remove DC offset from a received optical data signal. The circuit has a first capacitor coupled between a first terminal and a second terminal. A first resistance network is coupled between the second terminal and a reference voltage. A control circuit has a first output coupled to a control input of the first resistance network. The control circuit monotonically increases an effective resistance of the first resistance network to increase the dynamic time constant. The first resistance network has a resistor coupled to the second terminal, and a transistor with a first conduction terminal coupled to the resistor, a second conduction terminal coupled to the reference voltage, and a control terminal coupled to the first output of the control circuit. The first capacitor has a variable capacitance. The monotonic increase in the dynamic time constant can be linear or non-linear.

Claims (29)

1. A circuit for controlling a circuit time constant to achieve a substantially zero DC offset in an optical data signal, comprising:

a first variable capacitor coupled between a first terminal of the circuit and a second terminal of the circuit;

a first transistor including a first conduction terminal coupled to the second terminal of the circuit and a second conduction terminal coupled for receiving a common mode reference signal; and

a control circuit including a first output coupled to a control terminal of the first transistor, wherein an output signal of the control circuit monotonically increases a resistance between the first conduction terminal of the first transistor and second conduction terminal of the first transistor to increase the circuit time constant and achieve the substantially zero DC offset in the optical data signal.

2. The circuit of claim 1 , further including:

a second variable capacitor coupled between a third terminal of the circuit and a fourth terminal of the circuit; and

a second transistor including a first conduction terminal coupled to the fourth terminal of the circuit and a second conduction terminal coupled for receiving the common mode reference signal, wherein the control circuit includes a second output coupled to a control terminal of the second transistor to monotonically increase a resistance between the first conduction terminal of the second transistor and second conduction terminal of the second transistor to increase the circuit time constant and achieve the substantially zero DC offset in the optical data signal.

3. The circuit of claim 1 , wherein the monotonic increase in the circuit time constant is linear.

4. The circuit of claim 1 , wherein the monotonic increase in the circuit time constant is non-linear.

5. A circuit for controlling a circuit time constant in an optical data signal, comprising:

a first variable capacitor coupled between a first terminal of the circuit and a second terminal of the circuit;

a first transistor including a first conduction terminal coupled to the second terminal of the circuit and a second conduction terminal coupled for receiving a reference signal; and

a control circuit including a first output coupled to a control terminal of the first transistor to control the circuit time constant, wherein an output signal of the control circuit changes a resistance between the first conduction terminal of the first transistor and second conduction terminal of the first transistor to achieve the substantially zero DC offset in the optical data signal.

6. The circuit of claim 5 , further including:

a second variable capacitor coupled between a third terminal and a fourth terminal; and

a second transistor including a first conduction terminal coupled to the fourth terminal and a second conduction terminal coupled for receiving the reference signal, wherein the control circuit includes a second output coupled to a control terminal of the second transistor.

7. The circuit of claim 5 , wherein the monotonic increase in the circuit time constant is non-linear.

8. A method of making a circuit for controlling a circuit time constant in an optical data signal, comprising:

providing a first variable capacitor coupled between a first terminal of the circuit and a second terminal of the circuit;

providing a first transistor including a first conduction terminal coupled to the second terminal of the circuit and a second conduction terminal coupled for receiving a reference signal; and

providing a control circuit including a first output coupled to a control terminal of the first transistor to change a resistance between the first conduction terminal of the first transistor and second conduction terminal of the first transistor to control the circuit time constant.

9. The method of claim 8 , further including:

providing a second variable capacitor coupled between a third terminal and a fourth terminal; and

providing a transistor including a first conduction terminal coupled to the fourth terminal and a second conduction terminal coupled for receiving the reference signal, wherein the control circuit includes a second output coupled to a control terminal of the second transistor.

10. The method of claim 8 , wherein the monotonic increase in the circuit time constant is non-linear.

11. The circuit of claim 8 , wherein the reference signal is a common mode reference signal.

12. The circuit of claim 8 , wherein the monotonic increase in the circuit time constant is linear.

13. The circuit of claim 5 , wherein the reference signal is a common mode reference signal.

14. The circuit of claim 5 , wherein the monotonic increase in the circuit time constant is linear.

Assignments (3)
ASSIGNMENT OF PATENT SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (049894/0523) Recorded Feb 17, 2023
From: HSBC BANK USA, NATIONAL ASSOCIATION, AS RESIGNING AGENT
To: JPMORGAN CHASE BANK, N.A., AS SUCCESSOR AGENT
Reel/Frame 062784/0040 →
SECURITY INTEREST Recorded Jul 29, 2019
From: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.; SEMTECH EV, INC.; TRIUNE SYSTEMS, L.L.C.; TRIUNE IP, LLC
To: HSBC BANK USA, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049894/0523 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 9, 2019
From: VALENCIA, MIGUEL; VOGIATZIS, NIKOLAOS
To: SEMTECH CORPORATION
Reel/Frame 048286/0391 →
Continuity (1)
Related Publication 20200259485A1 · Aug 13, 2020