CMOS image sensor with improved column data shift readout

1. An imaging sensor comprising: a pixel array having a plurality of imaging pixel sensor cells arranged in a number H horizontal rows and a number N vertical columns, pixel cell data being read out on N column lines of the array through the action of control signal circuits;

a separate analog-to-digital conversion (ADC) circuit coupled on an input side to each column line and on an output side to a separate M-bit wide digital memory circuit, pixel cell data being stored on each memory circuit representing pixel cell data output from each column line;

a column data readout circuit comprising N M-bit data shifters, each M-bit data shifter having an M-bit wide output, and single pole double throw (SPDT) switches whose common terminals provide inputs to the M-bit data shifters, wherein a first switch state of the SPDT switches connects the input of their associated M-bit data shifters to their associated M-bit wide digital memory circuits and wherein a second switch state of the SPDT switches connects the input of their associated M-bit data shifters to an M-bit wide output bus from an adjacent M-bit data shifter;

an M-bit parallel data process and output driver circuit coupled to the M-bit data shifter associated with the last array column to output pixel cell data from the imaging sensor and wherein employing these components may enable the imaging sensor to consume reduced power and to generate reduced electromagnetic interference and to operate at increased frame rate.

2. The imaging sensor of claim 1 wherein the M-bit data shifter associated with the first array column comprises an associated SPDT switch wherein the second switch state provides no data input.

3. The imaging sensor of claim 2 wherein each of the M bit shifters comprise a “D flip flop” which will store and output whatever logic level is applied to an input data terminal so long as the clock input is HIGH and once the clock input goes LOW it will not change state and store whatever data was present on its output before the clock transition occurred.

4. A method to achieve image readout with the imaging sensor as recited in claim 2 with an increased frame rate with reduced electromagnetic interference and reduced power consumption having a sequence of transfer modes comprising the steps of:

storing a representation of each pixel cell of a row of pixels as M-bit data words in a row of M-bit column memory circuits;

closing the first switches of the SPDT switches and upon the rising edge of a timing clock transferring the M-bit data words into the M bit shifters of the M-bit data shifter circuits and then opening the first switch; and

closing the second switch of the SPDT switches and upon the next and subsequent rising edges of the timing clock transferring the M bit shifters of the M-bit data words from each M-bit data shifter circuit to the adjacent M-bit data shifter until all the data loaded into the M-bit data shifters, when the first switch was closed, is transferred out through the M-bit parallel data process and output driver circuit.

5. The imaging sensor of claim 4 wherein the number of adjacent digital memory circuits coupled to a single group readout circuit is 8 or a whole number multiple of 2 greater than 8 and less than 1024.

6. The imaging sensor of claim 4 wherein the number of adjacent digital memory circuits coupled to a single group readout is 2 X wherein X is a whole number between 3 and 10.

7. The imaging sensor of claim 1 wherein each M-bit data shifter comprises M bit shifters in a parallel circuit configuration wherein each bit shifter comprises a connected single pole double throw (SPDT) switch whose common terminal provides an input to the bit shifter and wherein a first switch state of the SPDT switch connects the input of its associated bit shifter to an associated similar bit line of the M-bit wide digital memory circuit and wherein a second switch state of the SPDT switch connects the input of its associated bit shifter to an associated similar bit line of the M-bit wide output bus from an adjacent M-bit data shifter.

8. The imaging sensor of claim 1 also comprising a timing clock used to coordinate the transfer of imaging data among the M-bit data shifters.

9. A method to achieve image readout with the imaging sensor as recited in claim 1 with an increased frame rate with reduced electromagnetic interference and reduced power consumption having a sequence of transfer modes comprising the steps of: storing a representation of each pixel cell of a row of pixels as M-bit data words in a row of M-bit column memory circuits; closing the first switch of the SPDT switches and upon the rising edge of a timing clock transferring the M-bit data words into the M-bit data shifter circuits and then opening the first switch; and closing the second switch of the SPDT switches and upon the next and subsequent rising edges of the timing clock transferring the M-bit data words from each M-bit data shifter circuits to the adjacent M-bit data shifter until all the data loaded into the M-bit data shifters when the first switch was closed is transferred out through the M-bit parallel data process and output driver circuit.

10. An imaging sensor comprising: a pixel array having a plurality of imaging pixel sensor cells arranged in a number H horizontal rows and a number N vertical columns, pixel cell data being read out on N column lines of the array through the action of control signal circuits;

a separate analog-to-digital conversion (ADC) circuit coupled on an input side to each column line and on an output side to a separate M-bit wide digital memory circuit, pixel cell data being stored on each memory circuit representing pixel cell data output from each column line; a number of group readout circuits each coupled to a number of adjacent digital memory circuits and each group readout circuit capable of transferring out digital memory data from each of the number of memory circuits, wherein the number of group readout circuits is sufficient to read out all of the N column lines of the array;

a column data readout circuit comprising M-bit data shifters, one coupled to each of the group readout circuits, and single pole double throw (SPDT) switches whose common terminals provide inputs to the M-bit data shifters, wherein a first switch state of the SPDT switches connects the input of their associated M-bit data shifters to their associated group readout circuit and wherein a second switch state of the SPDT switches connects the input of their associated M-bit data shifters to an M-bit wide output bus from an adjacent M-bit data shifter;

an M-bit parallel data process and output driver circuit coupled to the M-bit data shifter associated with the last array column to output pixel cell data from the imaging sensor and wherein employing these components may enable the imaging sensor to consume reduced power and to generate reduced electromagnetic interference and to operate at increased frame rate.