GPU based server in a distributed file system
View Patent ↗A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. A plurality of failure resilient stripes is distributed across the plurality of storage devices such that each of the plurality of failure resilient stripes spans a plurality of the storage devices. A graphics processing unit is operable to access data files from the failure resilient stripes, while bypassing a kernel page cache. Furthermore, these data files may be accessed in parallel by the graphics processing unit.
1. A system comprising:
a volatile memory device;
a plurality of non-volatile memory devices;
a computing device operable build a plurality of failure-protected stripes such that each of the plurality of failure-protected stripes comprises a plurality of storage blocks, wherein each storage block of the plurality of storage blocks is located in a different flash memory device in a group of flash memory devices of the plurality of flash memory devices, and wherein no two failure-protected stripes of the plurality of failure-protected stripes comprises a plurality of storage blocks located in the same group of flash memory devices; and
a graphics processing device operable to transfer the plurality of storage blocks to the volatile memory device while bypassing a kernel page cache, wherein the graphics processing device is operable to access the plurality of storage blocks in parallel.
2. The system of claim 1 , wherein the computing device and the graphics processing device are operably coupled via a PCIe interface.
3. The system of claim 1 , wherein the computing device and the graphics processing device are operably coupled via a network interface.
4. The system of claim 1 , wherein the graphics processing device comprises a backend that is operable to manage data in the volatile memory device.
5. The system of claim 1 , wherein the graphics processing device comprises a frontend that is operable to determine a location of data required for a graphics operation.
6. The system of claim 1 , wherein the graphics processing device is operated to receive data via a network interface.
7. The system of claim 1 , wherein the graphics processing device comprises a frontend that is operable to indicate to a graphics processing unit (GPU) that data required for a graphics operation is available in the volatile memory device.
8. The system of claim 1 , wherein the computing device is operable to determine that data required for a graphics operation is located in a failure-protected stripe that is led by a bucket in a backend of the computing device.
9. The system of claim 1 , wherein the computing device comprises a frontend that is operable to indicate to a graphics processing unit (GPU) that data required for a graphics operation is available in the volatile memory device.
10. A method comprising:
building a plurality of failure-protected stripes, using a computing device, such that each of the plurality of failure-protected stripes comprises a plurality of storage blocks, wherein each storage block of the plurality of storage blocks is located in a different flash memory device in a group of flash memory devices of a plurality of flash memory devices, and wherein no two failure-protected stripes of the plurality of failure-protected stripes comprises a plurality of storage blocks located in the same group of flash memory devices;
transferring the plurality of storage blocks to a volatile memory device while bypassing a kernel page cache, wherein transferring comprises transferring the plurality of storage blocks in parallel; and
performing a graphics operation on the transferred plurality of storage blocks using a graphics processing device.
11. The method of claim 10 , wherein the computing device and the graphics processing device are operably coupled via a PCIe interface.
12. The method of claim 10 , wherein the computing device and the graphics processing device are operably coupled via a network interface.
13. The method of claim 10 , wherein the graphics processing device comprises a backend that is operable to manage data in the volatile memory device.
14. The method of claim 10 , wherein the method comprises determining a location of data required for the graphics operation.
15. The method of claim 10 , wherein the method comprises receiving data, at the graphics processing device, via a network interface.
16. The method of claim 10 , wherein the method comprises indicating to a graphics processing unit (GPU) that data required for the graphics operation is available in the volatile memory device.
17. The method of claim 10 , wherein the method comprises determining, by the computing device, that data required for the graphics operation is located in a failure-protected stripe that is led by a bucket in a backend of the computing device.
18. The method of claim 10 , wherein the method comprises indicating, by a frontend of the computing device, that data required for the graphics operation is available in the volatile memory device.