IP Library Granted Patent US 11,152,385
Granted Patent B2
US 11,152,385 · App. 16/276,026 · Granted Oct 19, 2021

Stacked type semiconductor memory device and method for manufacturing the same

Inventors: Tatsuya Kato (Yokkaichi, JP); Wataru Sakamoto (Yokkaichi, JP); Fumitaka Arai (Yokkaichi, JP)
Assignee: Kioxia Corporation
H01L27/11556H01L27/11519H01L27/11548
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Quick Facts
Patent No.
US 11,152,385
App. No.
16/276,026
Granted
Oct 19, 2021
Kind
B2
Abstract

According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.

Claims (69)

1. A semiconductor memory device comprising:

a substrate;

a conductive layer being provided above the substrate;

a first select gate including a first portion extending in a first direction and a second portion electrically connecting to the first portion, the first select gate being provided above the conductive layer;

a second select gate including a third portion extending in the first direction and a fourth portion electrically connecting to the third portion, the second select gate being adjacent to the first select gate in a second direction crossing the first direction and provided above the conductive layer;

a third select gate including a fifth portion extending in the first direction and a sixth portion electrically connecting to the fifth portion, the sixth portion being provided at a different location from the fourth portion in the first direction and the second direction, the third select gate and the second select gate being arranged at the third portion in the second direction and provided above the conductive layer;

a first insulating layer being provided between the second portion and the fourth portion;

a first pillar being provided between the third portion and the fifth portion, an end portion of the first pillar being connected to the conductive layer, and the first pillar extending in a third direction crossing the first and second directions perpendicular to a surface of the substrate; and

a first select transistor being provided between the first pillar and the third portion.

2. The device according to claim 1 , further comprising:

a second select transistor being provided between the first pillar and the fifth portion.

3. The device according to claim 1 , further comprising:

a second insulating layer being in contact with an end portion, in the first direction, of the third portion,

wherein another end portion, in the first direction, of the third portion is in contact with the fourth portion.

4. The device according to claim 1 , further comprising:

a third insulating layer being in contact with an end portion, in the first direction, of the fifth portion,

wherein another end portion, in the first direction, of the fifth portion is in contact with the sixth portion.

5. The device according to claim 3 , wherein the second insulating layer is in contact with the fifth portion.

6. The device according to claim 1 , further comprising:

a fourth insulating layer being provided between the first portion and the third portion, the fourth insulating layer being in contact with the first insulating layer, the second portion and the fourth portion.

7. The device according to claim 1 , further comprising:

a fifth insulating layer being provided at a different location away from the first insulating layer in the first and the second directions and in contact with the sixth portion.

8. The device according to claim 1 , wherein

the second portion extends in the second direction toward the third portion,

a length of the second portion in the second direction is larger than a length of the first portion in the second direction,

the fourth portion extends in the second direction toward the first portion, and

a length of the fourth portion in the second direction is larger than a length of the third portion in the second direction.

9. The device according to claim 1 , further comprising:

a first contact being electrically connected to the second portion; and

a second contact being electrically connected to the fourth portion,

wherein the first contact is provided at a same location as the second contact in the second direction.

10. The device according to claim 9 , further comprising:

a third contact being electrically connected to the sixth portion and extending in the third direction,

wherein the second contact is provided at a different location from the third contact in the first direction.

11. The device according to claim 1 , further comprising:

a first control gate electrode film being provided between the first portion and the conductive layer and extending in the first direction;

a second control gate electrode film being provided between the third portion and the conductive layer and extending in the first direction; and

a third control gate electrode film being provided between the second portion and the conductive layer, the third control gate electrode film being provided between the fourth portion and the conductive layer, the third control gate electrode film extending in the second direction and being electrically connected to the first control gate electrode film and the second control gate electrode film.

12. The device according to claim 11 , further comprising:

a fourth control gate electrode film being provided between the fifth portion and the conductive layer and extending in the first direction;

a first memory cell being provided between the first pillar and the second control gate electrode film to store information; and

a second memory cell being provided between the first pillar and the fourth control gate electrode film to store information.

13. The device according to claim 1 , further comprising:

a first control gate electrode film being provided between the third portion and the conductive layer, and extending in the first direction;

a second control gate electrode film being provided between the fifth portion and the conductive layer, and extending in the first direction;

a first memory cell being provided between the first pillar and the first control gate electrode film to store information; and

a second memory cell being provided between the first pillar and the second control gate electrode film to store information.

14. The device according to claim 1 , further comprising:

a fourth select gate electrode including a seventh portion extending in the first direction and an eighth portion electrically connecting to the seventh portion, the fourth select gate electrode being next to the third select gate in the second direction and provided above the conductive layer;

a second pillar being adjacent to the first pillar in the second direction, and extending in the third direction; and

a third select transistor being provided between the fourth select gate electrode and the second pillar.

15. The device according to claim 14 , further comprising:

a third control gate electrode film being provided between the seventh portion and the conductive layer, and extending in the first direction; and

a third memory cell being provided between the second pillar and the third control gate electrode film to store information.

16. The device according to claim 11 , wherein the first control gate electrode film is longer than the first select gate in the first direction.

17. The device according to claim 13 , wherein the first control gate electrode film is longer than the second select gate in the first direction.

18. The device according to claim 11 , further comprising:

a first contact being electrically connected to the first select gate and extending in the third direction; and

a second contact being electrically connected to the first control gate electrode film and extending in the third direction,

wherein the second contact is longer than the first contact in the third direction.

19. The device according to claim 13 , further comprising:

a first contact being electrically connected to the second select gate and extending in the third direction; and

a second contact being electrically connected to the first control gate electrode film and extending in the third direction, wherein the second contact is longer than the first contact in the third direction.

20. The device according to claim 1 , wherein the first select transistor comprises the first pillar as a channel and the third portion as a gate.

21. The device according to claim 2 , wherein the second select transistor comprises the first pillar as a channel and the fifth portion as a gate.

22. The device according to claim 1 , wherein

the second portion extends in the second direction toward the third portion,

the fourth portion extends in the second direction toward the first portion, and

a distance between the first portion and the third portion in the second direction is larger than a distance between the second portion and the fourth portion in the second direction.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Sep 7, 2021
From: TOSHIBA MEMORY CORPORATION; K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 057425/0547 →
CHANGE OF NAME Recorded Sep 7, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 057425/0748 →
Continuity (4)
Continuation 15822860 · Nov 27, 2017
Continuation 14838854 · Aug 28, 2015
Provisional Application 62097982 · Dec 30, 2014
Related Publication 20190181151A1 · Jun 13, 2019