Semiconductor integrated circuit adapted to scan testing, and method of designing the same

1. A semiconductor integrated circuit, comprising:

a first scan flipflop comprising a first scan input, a first data input, a first selection input, and a first output, wherein the first scan flipflop is configured to:

output, on the first output, a value corresponding to the first scan input based on a first signal being received at the first selection input; and

output, on the first output, a value corresponding to the first data input based on a second signal being received at the first selection input; and

a second scan flipflop comprising a second scan input, a second data input, a second selection input, and a second output, wherein the second scan input is connected to the first output, wherein the second data input is configured to receive an unknown value, wherein the second selection input is configured to receive, based on the second data input corresponding to an unknown value, the first signal, and wherein the second scan flipflop is configured to output, on the second output, a value corresponding to the second scan input based on the first signal being received at the second selection input, wherein the value output on the second output corresponds to the value output on the first output.

2. The semiconductor integrated circuit according to claim 1 , further comprising:

a plurality of scan chains, wherein each scan chain comprises a plurality of scan flipflops, and wherein the first and second scan flipflops are part of one of the plurality of scan chains;

decompression circuitry configured to generate test data to be supplied to the plurality of scan chains by decompressing compressed test data; and

compression circuitry configured to generate compressed test result data based on output responses outputted from the plurality of scan chains.

3. The semiconductor integrated circuit according to claim 1 , further comprising:

a selector configured to cause the first signal to be received at the second selection input for a first type of scan test and to cause the second signal to be received at the second selection input for a second type of scan test.

4. The semiconductor integrated circuit according to claim 3 , further comprising:

a flipflop configured to output a value corresponding to a type of scan test;

wherein the selector is further configured to receive the outputted value corresponding to the type of scan test.

5. The semiconductor integrated circuit according to claim 3 , wherein the first type of scan test corresponds to AC scanning and the second type of scan test corresponds to DC scanning; or

wherein the first type of scan test corresponds to DC scanning and the second type of scan test corresponds to AC scanning.

6. The semiconductor integrated circuit according to claim 1 , further comprising:

a third scan flipflop comprising a third scan input, a third data input, a third selection input, and a third output, wherein the third data input is configured to receive a value for which a probability of the value being unknown is larger than 0% and less than 100%, and wherein the third scan flipflop is configured to:

output, on the third output, a value corresponding to the third scan input based on the first signal being received at the third selection input; and

output, on the third output, a value corresponding to the third data input based on the second signal being received at the third selection input; and

a selector configured to selectively cause the first signal or the second signal to be received at the third selection input.

7. A method of designing a semiconductor integrated circuit, comprising:

generating, by a device, a netlist of a semiconductor integrated circuit comprising at least one scan flipflop configured to capture a value inputted to a scan input of the at least one scan flipflop in a capture mode, wherein generating the netlist is based on one or more probabilities of one or more respective scan flipflops capturing an unknown value; and

implementing the semiconductor integrated circuit based on the netlist.

8. The method according to claim 7 , wherein generating the netlist comprises generating the netlist to supply a control signal asserted during a scan test to a scan enable terminal of the at least one scan flipflop.

9. The method according to claim 8 , wherein generating the netlist comprises generating the netlist to selectively supply a first signal or a second signal to the scan enable terminal of the at least one scan flipflop.

10. The method according to claim 9 , wherein generating the netlist further comprises generating the netlist to selectively supply the first signal or the second signal to the scan enable terminal of the at least one scan flipflop based on a type of the scan test.

11. The method according to claim 9 , wherein generating the netlist further comprises generating the netlist to selectively supply the first signal or the second signal to the scan enable terminal of the at least one scan flipflop based on the control signal, wherein the control signal is supplied from outside the semiconductor integrated circuit.

12. The method according to claim 7 , wherein generating the netlist comprises:

extracting a scan flipflop configured to capture an unknown value via a data input of the scan flipflop; and

generating the netlist to allow a first signal to be supplied to a scan enable terminal of the extracted scan flipflop.

13. The method according to claim 7 , wherein generating the netlist comprises:

determining a probability of a scan flipflop capturing an unknown value; and

generating the netlist to allow a first signal to be supplied to a scan enable terminal of the scan flipflop based on the probability.

14. The method according to claim 7 , wherein generating the netlist comprises:

inserting a plurality of scan chains comprising a scan chain comprising the at least one scan flipflop;

inserting decompression circuitry configured to generate test data to be supplied to the plurality of scan chains by decompressing compressed test data; and

inserting compression circuitry configured to generate compressed test result data based on output responses outputted from the plurality of scan chains.

15. A non-transitory tangible storage medium having processor-executable instructions stored thereon, wherein the processor-executable instructions, when executed, facilitate:

generating a netlist of a semiconductor integrated circuit comprising at least one scan flipflop configured to capture a value inputted to a scan input of the at least one scan flipflop in a capture mode, wherein generating the netlist is based on one or more probabilities of one or more respective scan flipflops capturing an unknown value; and

outputting data for implementing the semiconductor integrated circuit based on the netlist.

16. The non-transitory tangible storage medium according to claim 15 , wherein generating the netlist comprises generating the netlist to supply a control signal asserted during a scan test to a scan enable terminal of the at least one scan flipflop.

17. The non-transitory tangible storage medium according to claim 16 , wherein generating the netlist comprises generating the netlist to selectively supply a first signal or a second signal to the scan enable terminal of the at least one scan flipflop.

18. The non-transitory tangible storage medium according to claim 15 , wherein generating the netlist comprises:

extracting a scan flipflop configured to capture an unknown value via a data input of the scan flipflop; and

generating the netlist to allow a first signal to be supplied to a scan enable terminal of the extracted scan flipflop.

19. The non-transitory tangible storage medium according to claim 15 , wherein generating the netlist comprises:

determining a probability of a scan flipflop capturing an unknown value; and

generating the netlist to allow a first signal to be supplied to a scan enable terminal of the scan flipflop based on the probability.