Voltage regulator
A voltage regulator includes an error amplifier which receives a feedback voltage and a reference voltage, an amplifier circuit which receives an output voltage of the error amplifier and controls a gate of an output transistor by a first output voltage, and a non-regulation detection circuit which detects a non-regulation state of the voltage regulator based on a second output voltage of the amplifier circuit. The amplifier circuit includes a first transistor receiving the output voltage of the error amplifier at a gate of the first transistor, and a second transistor connected to a drain of the first transistor, and provides the second output voltage based on a gate-source voltage of the second transistor.
1. A voltage regulator, comprising: a feedback circuit configured to provide a feedback voltage based on an output voltage provided from an output transistor; an error amplifier configured to receive the feedback voltage and a reference voltage; an amplifier circuit configured to receive an output voltage from the error amplifier, amplify the output voltage from the error amplifier to generate a first output voltage, and control a gate of the output transistor with the first output voltage; and a non-regulation detection circuit configured to detect a non-regulation state of the voltage regulator based on a second output voltage provided from the amplifier circuit, the amplifier circuit comprising a first transistor receiving the output voltage of the error amplifier at a gate of the first transistor, and a second transistor connected to a drain of the first transistor, and providing the second output voltage based on a gate-source voltage of the second transistor, wherein the first output voltage is the voltage at a drain of the second transistor, wherein the amplifier circuit comprises a reference voltage circuit configured to supply a voltage to a gate of the second transistor.
2. The voltage regulator according to claim 1 , wherein the amplifier circuit comprises a constant current source configured to bias the second transistor.
3. The voltage regulator according to claim 1 , further comprising a second reference voltage circuit having a third transistor whose gate is connected to the gate of the second transistor and a second constant current source configured to bias the third transistor, the second reference voltage circuit being configured to supply a second reference voltage to the non-regulation detection circuit.
4. The voltage regulator according to claim 2 , further comprising a second reference voltage circuit having a third transistor whose gate is connected to the gate of the second transistor and a second constant current source configured to bias the third transistor, the second reference voltage circuit being configured to supply a second reference voltage to the non-regulation detection circuit.
5. The voltage regulator according to claim 1 , wherein the second transistor comprises an NMOS transistor, and wherein the first transistor comprises a PMOS transistor, wherein the drain of the second transistor is connected to a drain of the first transistor.
6. The voltage regulator according to claim 1 , wherein the second transistor comprises an NMOS transistor, and wherein the first transistor comprises an NMOS transistor, wherein a source of the second transistor is connected to a drain of the first transistor.
7. The voltage regulator according to claim 2 , wherein the constant current source is connected to a source of the second transistor.
8. The voltage regulator according to claim 7 , wherein the second transistor comprises an NMOS transistor, and wherein the first transistor comprises a PMOS transistor, wherein the drain of the second transistor is connected to a drain of the first transistor.
9. The voltage regulator according to claim 2 , wherein the constant current source is connected to the drain of the second transistor.
10. The voltage regulator according to claim 9 , wherein the second transistor comprises an NMOS transistor, and wherein the first transistor of the amplifier circuit comprises an NMOS transistor, wherein a source of the second transistor is connected to a drain of the first transistor.