IP Library Granted Patent US 11,127,681
Granted Patent B2
US 11,127,681 · App. 16/280,003 · Granted Sep 21, 2021

Three-dimensional memory including molybdenum wiring layer having oxygen impurity and method for manufacturing the same

Inventors: Satoshi Wakatsuki (Yokkaichi Mie, JP); Katsuaki Natori (Yokkaichi Mie, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L23/53257H01L27/11582H01L29/40117
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Quick Facts
Patent No.
US 11,127,681
App. No.
16/280,003
Granted
Sep 21, 2021
Kind
B2
Abstract

A semiconductor device includes a substrate. The semiconductor device further includes a wiring layer provided on the substrate, the wiring layer including a molybdenum layer including oxygen atoms as an impurity.

Claims (29)

1. A semiconductor device comprising:

a substrate; and

a wiring layer provided on the substrate, the wiring layer including a molybdenum layer containing oxygen atoms as an impurity,

wherein a particle diameter of a crystal grain of the wiring layer increases to 25 nanometers (nm) or more through incorporating the oxygen atoms.

2. The semiconductor device according to claim 1 , wherein a concentration of the oxygen atoms in the molybdenum layer is in a range of 1.0×10 20 atoms/centimeter (cm) 3 to 5.0×10 22 atoms/cm 3 .

3. The semiconductor device according to claim 1 , wherein the wiring layer comprises a plurality of electrode layers provided on the substrate, and the semiconductor device further comprises:

a plurality of insulating layers provided alternately with the plurality of electrode layers on the substrate;

a semiconductor layer embedded in the electrode layers and the insulating layers; and

a charge storage layer provided around the semiconductor layer.

4. The semiconductor device according to claim 1 , wherein a concentration of the oxygen atoms in the molybdenum layer is greater than 1.0×10 20 atoms/cm 3 .

5. The semiconductor device according to claim 1 , wherein a concentration of the oxygen atoms in the molybdenum layer is less than 5.0×10 22 atoms/cm 3 .

6. The semiconductor device according to claim 1 , wherein the wiring layer further comprising a metal layer different from the molybdenum layer, the metal layer having oxygen atoms.

7. A method for manufacturing a semiconductor device, the method including forming a wiring layer on a substrate, the wiring layer comprising a molybdenum layer including oxygen atoms as an impurity by oxidizing a metal layer different from the molybdenum layer such that the oxygen atoms are introduced from the metal layer into the molybdenum layer.

8. The method for manufacturing a semiconductor device, according to claim 7 , further comprising heating the molybdenum layer in an atmosphere containing oxygen such that the oxygen atoms are introduced into the molybdenum layer.

9. The method for manufacturing a semiconductor device, according to claim 7 , further comprising oxidizing and heating the molybdenum layer such that the oxygen atoms are introduced into the molybdenum layer.

10. The method for manufacturing a semiconductor device, according to claim 7 , further comprising, after forming the molybdenum layer including the oxygen atoms, decreasing a concentration of the oxygen atoms in the molybdenum layer.

11. The method for manufacturing a semiconductor device, according to claim 10 , wherein decreasing concentration of the oxygen atoms in the molybdenum layer comprises heating the molybdenum layer in an atmosphere containing hydrogen.

12. The method for manufacturing a semiconductor device, according to claim 11 , wherein the molybdenum layer is heated at a temperature in a range of 450° C. to 900° C. in the atmosphere containing hydrogen.

13. The method for manufacturing a semiconductor device, according to claim 11 , wherein the concentration of the oxygen atoms in the molybdenum layer is decreased to no less than 1.0×10 20 atoms/cm 3 .

14. The method for manufacturing a semiconductor device, according to claim 11 , wherein the concentration of the oxygen atoms in the molybdenum layer is decreased to less than 5.0×10 22 atoms/cm 3 .

15. The method for manufacturing a semiconductor device, according to claim 7 , wherein forming the wiring layer comprises forming a plurality of electrode layers alternately stacked with a plurality of insulating layers on the substrate, and the method further comprises:

forming a semiconductor layer embedded in the electrode layers and the insulating layers; and

forming a charge storage layer embedded in the semiconductor layer, the electrode layers and the insulating layers.

16. The method for manufacturing a semiconductor device, according to claim 7 , the method further comprising:

forming a plurality of first films alternately with a plurality of insulating layers on the substrate;

forming a charge storage layer in the first films and the insulating layers;

forming a semiconductor layer in the first films and the insulating layers;

removing the first films and forming a plurality of recess portions between the insulating layers; and

forming, as at least a portion of the wiring layer, a plurality of electrode layers in the recess portions.

Assignments (2)
CHANGE OF NAME AND ADDRESS Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058905/0582 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2019
From: WAKATSUKI, SATOSHI; NATORI, KATSUAKI
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 049485/0524 →
Priority Claims (1)
JP JP2018-173549 · Sep 18, 2018 · national
Continuity (1)
Related Publication 20200091080A1 · Mar 19, 2020