Multi-GHZ fully synthesizable CMOS fractional divider

1. An apparatus comprising:

a fractional divider circuit configured to generate a feedback clock signal in response to a selection signal, a divided clock signal and an output clock signal, wherein a synchronizer circuit is configured to synchronize said selection signal; and

a modulator circuit configured to generate said selection signal in response to said feedback clock signal, wherein (a) said fractional divider circuit generates four phase clock signals from said divided clock signal, (b) said four phase clock signals are interleaved by said fractional divider circuit to select one of said four phase clock signals as said feedback clock signal and (c) said selection signal is synchronized in response to said divided clock signal to generate said feedback clock signal.

2. The apparatus according to claim 1 , wherein said fractional divider circuit is a fully synthesizable CMOS device.

3. The apparatus according to claim 1 , wherein (i) said divided clock signal is generated by a fixed divide-by-4 divider circuit in response to said output clock signal and (ii) a frequency of said divided clock signal is one quarter of a frequency of said output clock signal.

4. The apparatus according to claim 1 , wherein said fractional divider circuit generates said four phase signals to produce divide numbers interleaving N, N+0.25, N+0.5 and N+0.75 to generate an average divider ratio.

5. The apparatus according to claim 1 , wherein said fractional divider circuit comprises a four phase generator and a multiplexer circuit.

6. The apparatus according to claim 5 , wherein said four phase generator generates said four phase clock signals from said divided clock signal using said output clock signal to synchronize with said divided clock signal.

7. The apparatus according to claim 5 , wherein (i) said multiplexer circuit (a) receives said four phase clock signals and (b) presents one of said four phase clock signals as said feedback clock signal in response to a synchronization signal and a ready signal and (ii) said synchronization signal and said ready signal are generated in response to said selection signal, said divided clock signal and a divider control signal.

8. The apparatus according to claim 5 , wherein said multiplexer circuit is configured implement a selection logic to interleave said four phase clock signals.

9. The apparatus according to claim 1 , further comprising a counter circuit configured to generate a ready signal and a synchronization signal for said fractional divider circuit, wherein said counter circuit implements a seven bit counter configured to reset after a pre-determined number of cycles.

10. The apparatus according to claim 1 , wherein (i) said output clock signal is generated in response to an input clock signal and (ii) a maximum frequency of said input clock signal is approximately 7 GHZ.

11. The apparatus according to claim 1 , wherein said fractional divider circuit is implemented using CMOS logic.

12. The apparatus according to claim 11 , wherein said CMOS logic is implemented without customized CMOS logic gates.

13. The apparatus according to claim 11 , wherein said CMOS logic is implemented using FinFET technology.

14. The apparatus according to claim 1 , wherein said apparatus reduces a chip-size area and an amount of power consumption compared to using at least one of (a) a calibration scheme, (b) current mode logic (CML) and (c) customized CMOS logic.

15. The apparatus according to claim 1 , wherein said fractional divider circuit operates at a divide-by-4 clock speed.

16. An apparatus comprising:

a fractional divider circuit configured to generate a feedback clock signal in response to a selection signal, a divided clock signal and an output clock signal; and

a modulator circuit configured to generate said selection signal in response to said feedback clock signal, wherein (a) said fractional divider circuit generates four phase clock signals from said divided clock signal, (b) said four phase clock signals are interleaved by said fractional divider circuit to select one of said four phase clock signals as said feedback clock signal, (c) said selection signal is synchronized in response to said divided clock signal to generate said feedback clock signal, (d) said fractional divider circuit comprises a four phase generator and multiplexer circuit and (e) said multiplexer circuit receives said four phase clock signals and presents one of said four phase clock signals as said feedback clock signal in response to a synchronization signal and a ready signal.

17. The apparatus according to claim 16 , wherein said fractional divider circuit is implemented using CMOS logic.

18. The apparatus according to claim 16 , wherein said fractional divider circuit operates at a divide-by-4 clock speed.

19. An apparatus comprising:

a fractional divider circuit configured to generate a feedback clock signal in response to a selection signal, a divided clock signal and an output clock signal;

a modulator circuit configured to generate said selection signal in response to said feedback clock signal, wherein (a) said fractional divider circuit generates four phase clock signals from said divided clock signal, (b) said four phase clock signals are interleaved by said fractional divider circuit to select one of said four phase clock signals as said feedback clock signal and (c) said selection signal is synchronized in response to said divided clock signal to generate said feedback clock signal; and

a counter circuit and a synchronizer circuit connected between said fractional divider circuit and said modulator circuit.

20. An apparatus comprising:

a fractional divider circuit configured to generate a feedback clock signal in response to a selection signal, a divided clock signal and an output clock signal; and

a modulator circuit configured to generate said selection signal in response to said feedback clock signal, wherein (a) said fractional divider circuit generates four phase clock signals from said divided clock signal, (b) said four phase clock signals are interleaved by said fractional divider circuit to select one of said four phase clock signals as said feedback clock signal, (c) said selection signal is synchronized in response to said divided clock signal to generate said feedback clock signal, (d) said fractional divider circuit comprises a four phase generator and a multiplexer circuit, (e) said multiplexer circuit (i) receives said four phase clock signals and (ii) presents one of said four phase clock signals as said feedback clock signal in response to a synchronization signal and a ready signal and (f) said synchronization signal and said ready signal are generated in response to said selection signal, said divided clock signal and a divider control signal.