Memory system
A memory system includes a memory chip, a queue block and a memory controller. The queue block is configured to store a command to be transmitted to the memory chip. The queue block includes a first queue and a plurality of second queues each corresponding to a plane of the memory chip. The memory controller is configured to determine whether or not a first command enqueued in the first queue is a first read command. The first read command is a command for executing read operation in the planes asynchronously. When the first command is the first read command, the memory controller transfers the first command to one of the second queues corresponding to a plane in which the first command is to be executed. The memory controller selects the first queue or the second queues as a source of a command to be transferred to the memory chip.
1. A memory system, comprising:
a memory chip including a plurality of planes;
a queue block configured to store a command to be transmitted to the memory chip,
the queue block including a first queue and a plurality of second queues, the second queues respectively corresponding to the planes of the memory chip; and
a memory controller configured to:
determine whether or not a first command enqueued in the first queue is a first read command, the first read command being a command for executing a read operation in the planes asynchronously;
when determining that the first command is the first read command, transfer the first command to one of the second queues corresponding to a plane in which the first command is to be executed;
when determining that the first command is not the first read command, refrain from transferring the first command from the first queue so that the first command remains in the first queue; and
select the first queue or the second queues as a command source to be transferred to the memory chip.
2. The memory system according to claim 1 , wherein
the memory controller is further configured to determine which of the first queue and the second queues is to be selected as the command source, depending on availability of the first queue or the second queues.
3. The memory system according to claim 2 , wherein
the memory controller is configured to select the second queues as the command source when any of the second queues contains a command, and select the first queue as the command source when none of the second queues contains a command and the first queue contains a command.
4. The memory system according to claim 3 , wherein
when one or more commands are enqueued in the first queue, the first command is one of the one or more commands located at the head of the first queue.
5. The memory system according to claim 1 , wherein
the first queue includes a third queue and a fourth queue, and
the memory controller is further configured to:
store a third command in the third queue and store a fourth command in the fourth queue, the third command being other than the first read command, the fourth command being the first read command; and
transfer the fourth command from the fourth queue to one of the second queues, the one second queue corresponding to a plane in which the fourth command stored in the fourth queue is to be executed.
6. The memory system according to claim 5 , wherein
when any of the second queues contains the fourth command, the memory controller selects the second queues as the command source.
7. The memory system according to claim 5 , wherein
when the fourth command is stored in any of the second queues during execution of the third command in the memory chip, the memory controller suspends the execution of the third command and selects the second queues as the command source.
8. The memory system according to claim 1 , wherein
the memory controller determines whether or not the memory chip is in write or erase operation, and, when determining that the memory chip is not in write or erase operation, determines which of the first queue and the second queues is to be selected as the command source.
9. A method of controlling a memory system,
the memory system including:
a memory chip including a plurality of planes; and
a queue block configured to store a command to be transmitted to the memory chip,
the queue block including a first queue and a plurality of second queues, the second queues respectively corresponding to the planes of the memory chip;
the method comprising:
determining whether or not a first command enqueued in the first queue is a first read command, the first read command being a command for executing a read operation in the planes asynchronously;
transferring, when determining that the first command is the first read command, the first command to one of the second queues corresponding to a plane in which the first command is to be executed;
refraining, when determining that the first command is not the first read command, from transferring the first command from the first queue so that the first command remains in the first queue; and
selecting the first queue or the second queues as a command source to be transferred to the memory chip.
10. The method according to claim 9 , further comprising
determining which of the first queue and the second queues is to be selected as the command source, depending on availability of the first queue or the second queues.
11. The method according to claim 10 , further comprising:
selecting the second queues as the command source when any of the second queues contains a command; and
selecting the first queue as the command source when none of the second queues contains a command and the first queue contains a command.
12. The method according to claim 11 , wherein
when one or more commands are enqueued in the first queue, the first command is one of the one or more commands located at the head of the first queue.
13. The method according to claim 9 , wherein
the first queue includes a third queue and a fourth queue, and
the method further comprises:
storing a third command in the third queue, the third command being other than the first read command;
storing a fourth command in the fourth queue, the fourth command being the first read command; and
transferring the fourth command from the fourth queue to one of the second queues, the one second queue corresponding to a plane in which the fourth command stored in the fourth queue is to be executed.
14. The method according to claim 13 , further comprising
selecting, when any of the second queues contains the fourth command, the second queues as the command source.
15. The method according to claim 13 , further comprising
suspending, when the fourth command is stored in any of the second queues during execution of the third command in the memory chip, the execution of the third command and selecting the second queues as the command source.
16. The method according to claim 9 , further comprising:
determining whether or not the memory chip is in write or erase operation; and
determining, when determining that the memory chip is not in write or erase operation, which of the first queue and the second queues is to be selected as the command source.