Standby voltage condition for fast RF amplifier bias recovery

1. A circuital arrangement comprising:

a transistor stack configured to operate as an amplifier, the transistor stack comprising an input transistor and one or more cascode transistors comprising an output transistor;

a biasing circuit comprising a replica circuit of the transistor stack, the biasing circuit configured to provide an input gate biasing voltage to the input transistor and to a corresponding first transistor of the replica circuit,

wherein the circuital arrangement is configured to operate in at least an active mode for amplification of a radio frequency (RF) signal through the transistor stack, and a standby mode for essentially no current conduction through the transistor stack and for a reduced power consumption of the circuital arrangement,

wherein during operation in the active mode, the biasing circuit generates the input gate biasing voltage based on a reference current conducted through the replica circuit,

wherein the biasing circuit generates biasing voltages to one or more cascode transistors of the replica circuit that are substantially equal to biasing voltages to respective one or more cascode transistors of the transistor stack during operation in the active mode and during operation in the standby mode, and

wherein the biasing circuit generates biasing voltages to the one or more cascode transistors of the replica circuit during operation in the standby mode that are substantially equal to biasing voltages to the one or more cascode transistors of the replica circuit during operation in the active mode.

2. The circuital arrangement according to claim 1 , wherein:

the transistor stack is configured to operate between a first supply voltage coupled to the output transistor and a reference voltage coupled to the input transistor, and

the replica circuit is configured to operate between a second supply voltage coupled to a last transistor of the replica circuit in correspondence of the output transistor, and the reference voltage coupled to the first transistor.

3. The circuital arrangement according to claim 1 , wherein voltages at common source-drain nodes of the replica circuit during operation in the active mode are within 0.5 V of respective voltages during operation in the standby mode.

4. The circuital arrangement according to claim 1 , wherein the transistor stack is configured to amplify a radio frequency (RF) signal used for WiFi communication.

5. The circuital arrangement according to claim 4 , wherein the circuital arrangement is used in an electronic device used for WiFi communication.

6. The circuital arrangement according to claim 1 , wherein gates of transistors of the replica circuit and gates of the plurality of stacked transistors of the transistor stack are provided with same biasing voltages.

7. The circuital arrangement according to claim 1 , wherein gates of transistors of the replica circuit and gates of transistors of the transistor stack are provided with different biasing voltages.

8. The circuital arrangement according to claim 1 , wherein a height of a transistor stack of the replica circuit is equal to a height of the transistor stack configured to operate as an amplifier.

9. The circuital arrangement according to claim 1 , wherein a height of a transistor stack of the replica circuit is different form a height of the transistor stack configured to operate as an amplifier.

10. The circuital arrangement according to claim 1 , wherein transistors of the replica circuit and transistors of the transistor stack are floating transistors.

11. The circuital arrangement according to claim 1 , wherein transistors of the replica circuit and transistors of the transistor stack are body tied transistors.

12. The circuital arrangement according to claim 1 , wherein transistors of the replica circuit and/or transistors of the transistor stack comprise a combination of body tied transistors and floating transistors.

13. The circuital arrangement according to claim 1 , further comprising one or more gate capacitors each connected between a gate of a transistor of the one or more cascode transistors, wherein the each gate capacitor is configured to allow a gate voltage at the gate to vary along with a radio frequency (RF) voltage at a drain of the transistor.

14. The circuital arrangement according to claim 13 , wherein the one or more gate capacitors are configured to substantially equalize an output RF voltage at a drain of the output transistor across transistors of the transistor stack.

15. The circuital arrangement according to claim 2 , wherein the input gate biasing voltage during operation in the standby mode is substantially equal to the reference voltage.

16. The circuital arrangement according to claim 1 , wherein transistors of the replica circuit are reduced size versions by a factor N of corresponding transistors of the transistor stack, where N is in a range from 100 to 1000.

17. A communication device used for WiFi communication, the communication device comprising the circuital arrangement according to claim 1 .

18. The communication device according to claim 17 , wherein the communication device is a mobile handset.

19. A method for biasing a transistor stack configured to operate as an amplifier using a replica circuit of the transistor stack, the method comprising:

during an active amplification mode of operation of the amplifier:

regulating a biasing voltage to an input transistor of the transistor stack by conducting a reference current through the replica circuit; and

providing biasing voltages to cascode transistors of the replica circuit that are substantially equal to biasing voltages provided to cascode transistors of the transistor stack; and

during a standby mode of operation of the amplifier:

setting the biasing voltage to the input transistor to a fixed value so as essentially no current is conducted through the replica circuit; and

providing biasing voltages to the cascode transistors of the replica circuit that are substantially equal to biasing voltages provided to the cascode transistors of the transistor stack,

wherein the biasing voltages provided to the cascode transistors of the replica circuit during operation in the standby mode are substantially equal to the biasing voltages provided to the cascode transistors of the replica circuit during operation in the active mode.

20. The method according to claim 19 , wherein:

the transistor stack is configured to operate between a first supply voltage coupled to an output transistor of the transistor stack and a reference voltage coupled to the input transistor, and

the replica circuit is configured to operate between a second supply voltage coupled to a last transistor of the replica circuit in correspondence of the output transistor, and the reference voltage coupled to the first transistor.