Semiconductor integrated circuit including a regulator circuit

1. A semiconductor integrated circuit comprising:

an output transistor electrically connected between the power supply side first node and the output-side second node

an error amplifier having a first input terminal that is electrically connected to a third node between the second node and a standard potential, a second input terminal that is electrically connected to a reference voltage, and an output terminal that is electrically connected to a gate of the output transistor;

a replica transistor electrically connected between the first node and a fourth node that is different from the second node and constitutes a circuit that is configured to operate to correspond to the output transistor;

a current-limiting circuit having

an input node that is electrically connected to a fifth node between the fourth node and a first current source, wherein the fifth node is directly connected to the first current source, and

an output node that is electrically connected to a gate of the output transistor and a gate of the replica transistor; and

a potential regulation circuit electrically connected to the second node and the fourth node.

2. The semiconductor integrated circuit according to claim 1 , wherein

the potential regulation circuit is configured to make a potential of the second node equal to a potential of the fourth node.

3. The semiconductor integrated circuit according to claim 2 , wherein

the potential regulation circuit includes

a voltage follower having a first input terminal that is electrically connected to the second node, a first output terminal that is electrically connected to a second input terminal and the fourth node, and a second output terminal that is electrically connected to the fifth node.

4. The semiconductor integrated circuit according to claim 3 , wherein

the voltage follower includes:

a second error amplifier having a first input terminal that is electrically connected to the second node and a second input terminal that is electrically connected to the fourth node; and

a PMOS transistor having a gate that is connected to an output terminal of the second error amplifier, a source that is electrically connected to the fourth node, and a drain that is electrically connected to the first current source.

5. The semiconductor integrated circuit according to claim 4 , wherein the second error amplifier is configured to control a potential of the second node and the fourth node to be equal.

6. The semiconductor integrated circuit according to claim 2 , wherein

the potential regulation circuit includes

a current mirror circuit having a sense side that is electrically connected between the second node and a second current source and a mirror side that is electrically connected between the fourth node and the first current source.

7. The semiconductor integrated circuit according to claim 1 , wherein the output transistor and the replica transistor are PMOS transistors.

8. The semiconductor integrated circuit according to claim 1 , wherein a current of the output transistor is less than a current of the replica transistor.

9. A semiconductor integrated circuit comprising:

an output transistor electrically connected between a first node and a second node;

a replica transistor electrically connected between the first node and a third node that is different from the second node and constitutes a circuit that is configured to operate to correspond to the output transistor

a current-limiting circuit having an input node that is electrically connected to a fourth node between the third node and a first current source, wherein the fourth node is directly connected to the first current source, and a n output node that is electrically connected to a gate of the output transistor and a gate of the re plica transistor; and

a potential regulation circuit electrically connected to the second node and the third node.

10. The semiconductor integrated circuit according to claim 9 , wherein

the potential regulation circuit is configured to make a potential of the second node equal to a potential of the third node.

11. The semiconductor integrated circuit according to claim 10 , wherein

the potential regulation circuit includes

a voltage follower having a first input terminal that is electrically connected to the second node, a first output terminal that is electrically connected to a second input terminal and the third node, and a second output terminal that is electrically connected to the fourth node.

12. The semiconductor integrated circuit according to claim 11 , wherein

the voltage follower includes:

an error amplifier having a first input terminal that is electrically connected to the second node and a second input terminal that is electrically connected to the third node; and

a PMOS transistor having a gate that is connected to an output terminal of the error amplifier, a source that is electrically connected to the third node, and a drain that is electrically connected to the first current source.

13. The semiconductor integrated circuit according to claim 12 , wherein the second error amplifier is configured to control a potential of the second node and the fourth node to be equal.

14. The semiconductor integrated circuit according to claim 10 , wherein

the potential regulation circuit includes

a current mirror circuit having a sense side that is electrically connected between the second node and a second current source and a mirror side that is electrically connected between the third node and the first current source.

15. The semiconductor integrated circuit according to claim 9 , wherein the output transistor and the replica transistor are PMOS transistors.

16. The semiconductor integrated circuit according to claim 9 , wherein a current of the output transistor is less than a current of the replica transistor.

17. The semiconductor integrated circuit according to claim 1 , further comprising:

a PMOS transistor having a source that is electrically connected to the fourth node, and a drain that is electrically connected to the first current source.