Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes a substrate including wiring at a surface thereof, a semiconductor element on a surface of the substrate, a first solder resist on the wiring, a bonding wire connecting the wiring and the semiconductor element, and a second solder resist. The first solder resist has an opening region at which a part of the wiring is non-covered by the first solder resist, and the bonding wire connects the wiring and the semiconductor element in the opening region. The second solder resist at least partially covers the non-covered part of the wiring in the opening region.
1. A semiconductor device comprising:
a substrate including wiring at a surface thereof;
a semiconductor element on a surface of the substrate;
a first solder resist on the wiring, the first solder resist having an opening region at which a part of the wiring is non-covered by the first solder resist;
a bonding wire connecting the wiring and the semiconductor element in the opening region; and
a second solder resist at least partially covering the non-covered part of the wiring in the opening region,
wherein a thickness of the second solder resist is less than a width of the bonding wire at a connection region at which the bonding wire is connected to the wiring of the substrate.
2. The semiconductor device according to claim 1 , wherein a thermal expansion coefficient of the first solder resist and a thermal expansion coefficient of the second solder resist are substantially the same.
3. The semiconductor device according to claim 1 , wherein a thermal expansion coefficient β1 of the first solder resist and a thermal expansion coefficient β2 of the second solder resist satisfy 2|β1−β2|/(β1+β2)≤0.05.
4. The semiconductor device according to claim 1 , wherein a thermal expansion coefficient β1 of the first solder resist and a thermal expansion coefficient β2 of the second solder resist satisfy 2|β1−β2|/(β1+β2)≤0.03.
5. The semiconductor device according to claim 1 , wherein the second solder resist entirely covers the non-covered part of the wiring in the opening region.
6. The semiconductor device according to claim 1 , wherein the second solder resist at least covers a region of the non-covered part of the wiring at which the bonding wire is connected.
7. The semiconductor device according to claim 1 , further comprising:
an insulating resin layer on the semiconductor element, the first solder resist, and the second solder resist, the insulating resin layer containing a filler.
8. The semiconductor device according to claim 1 , wherein a part of the first solder resist and a part of the second solder resist are overlaid.
9. The semiconductor device according to claim 1 , wherein the second solder resist covers the first solder resist.
10. The semiconductor device according to claim 1 , wherein the second solder resist fills the opening region.
11. The semiconductor device according to claim 1 , wherein a gap is provided between the semiconductor element and the second solder resist.
12. The semiconductor device according to claim 1 , wherein the second solder resist covers the semiconductor element.
13. The semiconductor device according to claim 1 , wherein the semiconductor device is of a ball grid array (BGA) type.
14. The semiconductor device according to claim 1 , wherein the semiconductor device is of a land grid array (LGA) type.
15. A method of manufacturing a semiconductor device comprising:
preparing a device including a substrate including wiring at a surface thereof, a semiconductor element on a surface of the substrate, and a first solder resist on the wiring, the first solder resist having an opening region at which a part of the wiring is exposed;
connecting the wiring and the semiconductor element with a bonding wire in the opening region of the first solder resist; and
at least partially covering the exposed part of the wiring in the opening region with a second solder resist,
wherein a thermal expansion coefficient β1 of the first solder resist and a thermal expansion coefficient β2 of the second solder resist satisfy 2|β1−β2|/(β1+β2)≤0.05.
16. The method according to claim 15 , wherein a thermal expansion coefficient of the first solder resist and a thermal expansion coefficient of the second solder resist are substantially the same.
17. The method according to claim 15 , further comprising:
covering the semiconductor element, the first solder resist, and the second solder resist with an insulating resin layer containing a filler.
18. A semiconductor device comprising:
a substrate including wiring at a surface thereof;
a semiconductor element on a surface of the substrate;
a first solder resist on the wiring, the first solder resist having an opening region at which a part of the wiring is non-covered by the first solder resist;
a bonding wire connecting the wiring and the semiconductor element in the opening region; and
a second solder resist at least partially covering the non-covered part of the wiring in the opening region,
wherein a gap is provided between the semiconductor element and the second solder resist, and the second solder resist is not formed under the semiconductor element.
19. The semiconductor device according to claim 18 , wherein a maximum height of the second solder resist is lower than a maximum height of the semiconductor element.