Asymmetric correlated electron switch operation
Subject matter disclosed herein may relate to correlated electron switches that are capable of asymmetric set or reset operations.
1. A method comprising:
applying a first programming signal to first and second terminals of a correlated electron switch (CES) device to meet a first voltage condition or a first current condition, or a combination thereof, for placement of the CES device in a first impedance state, wherein the CES device comprises one or more layers of a correlated electron material (CEM) disposed between the first and second terminals;
applying a second programming signal to first and second terminals of the CES device to place the CES device in a second impedance state; and
applying a third programming signal to first and second terminals of the CES device to meet a second voltage condition or a second current condition, or a combination thereof, for placement of the CES device in the first impedance state,
wherein a polarity of the first voltage condition is opposite a polarity of the second voltage condition, and a polarity of the first current condition is opposite a polarity of the second current condition, and
wherein a difference in a magnitude of the first voltage condition and a magnitude of the second voltage condition or a difference in a magnitude of the first current condition and a magnitude of the second current condition, or any combination thereof, is responsive at least in part to a non-uniform application of a dopant to the one or more layers of the CEM disposed between the first and second terminals.
2. The method of claim 1 , wherein the first impedance state comprises a conductive or low impedance state and the second impedance state comprises an insulative or low impedance state, and wherein the first programming signal is applied in a first set operation, the second programming signal is applied in a reset operation and the third programming signal is applied in a second set operation.
3. The method of claim 2 , wherein the first set operation is characterized by a first set voltage condition and the second set operation is characterized by a second set voltage condition, and wherein a magnitude of the first set voltage condition is greater than a magnitude of the second set voltage condition.
4. The method of claim 2 , wherein the first set operation is characterized by a first set current condition and the second set operation is characterized by a second set current condition, and wherein a magnitude of the first set current condition is greater than a magnitude of the second set current condition.
5. The method of claim 2 , wherein application of the first programming signal to the first and second terminals of the CES device and application of the third programming signal to the first and second terminals of the CES device comprise injection of electrons in the CEM to achieve a sufficient concentration of electrons in the CEM to place the CES device in the conductive or low impedance state.
6. The method of claim 1 , wherein the first impedance state comprises an insulative or high impedance state and the second impedance state comprises a conductive or low impedance state, and wherein first programming signal is applied in a first reset operation, the second programming signal is applied in a set operation and the third programming signal is applied in a second reset operation.
7. The method of claim 1 , wherein the CES device is placed in the first impedance state or the second impedance state based, at least in part, on a localization of electrons in the CEM.
8. The method of claim 1 , wherein the CES device comprises a non-volatile memory device.
9. The method of claim 1 , wherein a majority a contiguous portion of the CEM is switchable between a conductive or low impedance state and an insulative or high impedance state to place the CES device in either the first impedance state or the second impedance state.
10. The method of claim 9 , wherein a majority a contiguous portion of the CEM is switchable between the conductive or low impedance state and the insulative or high impedance state responsive to a Mott transition.
11. The method of claim 9 , wherein the CEM comprises a transition metal oxide that is non-uniformly doped with an extrinsic ligand.
12. The method of claim 1 , wherein the CES device comprises a variable impeder device, and wherein the first impedance state imparts a first capacitance value and the second impedance state imparts a second capacitance value.
13. The method of claim 1 , wherein the one or more layers of the CEM comprise one or more contiguous layers of the CEM, and wherein the one or more contiguous layers of the CEM further comprises at least one layer of intrinsic CEM and one or more doped layers of CEM.
14. The method of claim 1 , wherein the one or more layers of the CEM comprise one or more contiguous layers of the CEM, and wherein the one or more contiguous layers of CEM comprise at least an intrinsic layer of CEM formed between an N-type doped layer of CEM and a P-type doped layer of CEM.
15. The method of claim 1 , wherein the one or more layers of the CEM comprise one or more contiguous layers of the CEM, and wherein the one or more contiguous layers of the CEM comprise at least an intrinsic layer of CEM formed between a first P-type doped layer of CEM and a second P-type doped layer of CEM, wherein a thickness of the first P-type doped layer of CEM is greater than a thickness of the second P-type doped layer of CEM.