IP Library Granted Patent US 10,839,911
Granted Patent B2
US 10,839,911 · App. 16/284,928 · Granted Nov 17, 2020

Semiconductor memory device and data writing method

Inventors: Tatsuo Ogura (Yokkaichi Mie, JP); Hideto Horii (Yokohama Kanagawa, JP)
Assignee: TOSHIBA MEMORY CORPORATION
G11C16/10G11C8/14G11C16/08G11C16/24H01L27/1157H01L27/11582
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Quick Facts
Patent No.
US 10,839,911
App. No.
16/284,928
Granted
Nov 17, 2020
Kind
B2
Abstract

A semiconductor memory device includes a plurality of memory cells, a plurality of word lines connected to the plurality of memory cells, respectively, and a row control circuit. The row control circuit is configured to apply a program voltage to a first word line among the word lines while stepping up a value of the program voltage; apply a first pass voltage to a second word line among the word lines different from the first word line when applying the program voltage having a voltage value equal to or greater than a predetermined voltage value to the first word line; and apply a second pass voltage having a voltage value higher than the first pass voltage to the second word line when applying the program voltage having a voltage value less than the predetermined voltage value to the first word line.

Claims (31)

1. A semiconductor memory device comprising:

a plurality of memory cells;

a plurality of word lines connected to the plurality of memory cells, respectively; and

a row control circuit configured to:

apply a program voltage to a first word line among the word lines while stepping up a value of the program voltage;

apply a first pass voltage to a second word line among the word lines different from the first word line when applying the program voltage having a voltage value equal to or greater than a predetermined voltage value to the first word line; and

apply a second pass voltage having a voltage value higher than the first pass voltage to the second word line when applying the program voltage having a voltage value less than the predetermined voltage value to the first word line.

2. The semiconductor memory device according to claim 1 ,

wherein the row control circuit is configured to variably control a voltage value corresponding to a step-up width of the program voltage according to an application control of the first pass voltage and the second pass voltage.

3. The semiconductor memory device according to claim 2 , wherein the row control circuit is configured to control the step-up width of the program voltage such that a first step-up width of the program voltage in a first step of the variable control is smaller than a second step-up width of the program voltage in a second step of the variable control.

4. The semiconductor memory device according to claim 3 , wherein the row control circuit is configured to control the step-up width of the program voltage such that a third step-up width of the program voltage in a third step of the variable control implemented after the first step and before the second step is larger than the second step-up width.

5. The semiconductor memory device according to claim 1 ,

wherein the row control circuit is configured to variably control a pulse width of the program voltage according to an application control of the first pass voltage and the second pass voltage.

6. The semiconductor memory device according to claim 5 ,

wherein the row control circuit is configured to narrow the pulse width of the program voltage by a predetermined time while the application control of the second pass voltage is performed and to widen the pulse width of the program voltage by a predetermined time while the application control of the first pass voltage is performed.

7. The semiconductor memory device according to claim 1 ,

wherein the row control circuit is configured to write multi-value data to a memory cell among the memory cells that is connected to the selected first word line.

8. A data writing method for performing writing of data with respect to a semiconductor memory device including a plurality of memory cells and a plurality of word lines connected to the plurality of memory cells, respectively, the data writing method comprising:

selecting a first word line among the words lines;

applying a program voltage to the selected first word line while stepping up a value of the program voltage;

applying a first pass voltage to a second word line among the word lines different from the first word line, when applying the program voltage having a voltage value equal to or greater than a predetermined value to the first world line; and

applying a second pass voltage having a voltage value higher than the first pass voltage to the second word line when applying the program voltage having a voltage value less than the predetermined voltage value to the first word line.

9. The data writing method according to claim 8 , further comprising:

variably controlling a voltage value corresponding to a step-up width of the program voltage according to an application control of the first pass voltage and the second pass voltage.

10. The data writing method according to claim 9 , wherein variably controlling the voltage value corresponding to the step-up width of the program voltage is performed such that a first step-up width of the program voltage in a first step of the variable control is smaller than a second step-up width of the program voltage in a second step of the variable control.

11. The data writing method according to claim 10 , wherein variably controlling the voltage value corresponding to the step-up width of the program voltage is performed such that a third step-up width of the program voltage in a third step of the variable control implemented after the first step and before the second step is larger than the second step-up width.

12. The data writing method according to claim 8 , further comprising:

variably controlling a pulse width of the program voltage according to an application control of the first pass voltage and the second pass voltage.

13. The data writing method according to claim 12 ,

wherein in variably controlling the pulse width, the pulse width of the program voltage is narrowed by a predetermined time while the application control of the second pass voltage is performed and the pulse width of the program voltage is widened by a predetermined time while the application control of the first pass voltage is performed.

14. The data writing method according to claim 8 , further comprising writing multi-value data to a memory cell among the memory cells that is connected to the selected first word line.

Assignments (2)
CHANGE OF NAME AND ADDRESS Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058905/0582 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2019
From: OGURA, TATSUO; HORII, HIDETO
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 048430/0604 →