Method and apparatus for improving integrity of processor voltage supply with support for DVFS

1. Circuitry for compensating for voltage droop in power supplied to a load, comprising:

a first low pass filter with a first time constant configured to filter a signal indicative of voltage provided to the load to provide a first low pass filtered signal;

a second low pass filter with a second time constant configured to filter the signal indicative of voltage provided to the load to provide a second low pass filtered signal, the second time constant less than the first time constant;

an offset generator configured to generate at least one voltage level that is a percentage of the first low pass filtered signal indicative of voltage provided to the load;

a first sensor configured to determine that the second low pass filtered signal is less than the at least one voltage level; and

control circuitry configured to activate at least one switch coupling a higher voltage source supply to the load in response to the first sensor determining that the second low pass filtered signal is less than the at least one voltage level.

2. The circuitry of claim 1 , further comprising a third low pass filter with a third time constant, the third time constant less than the first time constant and greater than the second time constant, the third low pass filter configured to filter the signal indicative of voltage provided to the load to provide a third low pass filtered signal; and

a second sensor configured to determine that the second low pass filtered signal is greater than the third low pass filtered signal;

wherein the control circuitry is further configured to disable activation of the at least one switch coupling a higher voltage source supply to the load in response to the second low pass filtered signal being greater than the third low pass filtered signal.

3. The circuitry of claim 2 , wherein the first time constant is 100 times the second time constant, and the third time constant is 10 times the second time constant.

4. The circuitry of claim 2 , wherein each of the first low pass filter, second low pass filter, and third low pass filter include a variable resistance.

5. The circuitry of claim 1 , wherein the offset generator is configured to generate additional voltage levels, each a different percentage of the first low pass filtered signal indicative of voltage provided to the load; and

further comprising additional sensors, each configured to determine that the second low pass filtered signal is less than a corresponding one of the additional voltage levels; and

wherein the at least one switch coupling the higher voltage source supply to the load comprises a plurality of switches; and

wherein the control circuitry is configured to activate a number of the switches based on a number of the first sensor and additional sensors determining that the second low pass filtered signal is less than the at least one voltage level or the additional voltage levels.

6. The circuitry of claim 5 , wherein the control circuitry is configured to disable the switches in a ramping manner over time.

7. The circuitry of claim 5 , wherein the control circuitry is configured to activate at least some of the switches for at most a predetermined maximum consecutive time.

8. A method of compensating for voltage droop in power supplied to a load, comprising:

determining that a signal indicative of voltage supplied to the load, to provide power to the load, is less than at least one predetermined percentage of a delayed version of the signal indicative of voltage supplied to the load;

in response to determining that the signal indicative of voltage supplied to the load is less than the at least one predetermined percentage of the delayed version of the signal indicative of voltage supplied to the load, coupling a higher voltage source supply to a higher level voltage rail providing power to the load.

9. The method of claim 8 , wherein the at least one predetermined percentage is a fixed percentage.

10. The method of claim 8 , wherein the at least one predetermined percentage is a programmable percentage.

11. The method of claim 8 , wherein the delayed version of the signal indicative of voltage supplied to the load comprises the signal indicative of voltage supplied to the load passed through a low pass filter.

12. The method of claim 8 , wherein the signal indicative of voltage supplied to the load comprises a first signal from the higher level voltage rail passed through a first low pass filter, and the delayed version of the signal indicative of voltage supplied to the load comprises a second signal from the higher level voltage rail passed through a second low pass filter, and a time constant of the first low pass filter is less than a time constant of the second low pass filter.

13. The method of claim 8 , wherein the at least one predetermined percentage of the delayed version of the signal indicative of voltage supplied to the load comprises a plurality of predetermined percentages, and wherein an extent of coupling of the higher voltage source supply to the higher level voltage rail is based on a number of instances for which the for which the signal indicative of voltage supplied to the load is less than various ones of the predetermined percentages of the delayed version of the signal indicative of voltage supplied to the load.

14. The method of claim 13 , further comprising generating an activation code based on the number of instances for which the signal indicative of voltage supplied to the load is less than various ones of the predetermined percentages of the delayed version of the signal indicative of voltage supplied to the load, and wherein the activation code is used in activating switches coupling the higher voltage source supply to the higher level voltage rail.

15. The method of claim 14 , further comprising determining that the signal indicative of voltage supplied to the load is greater than a further delayed version of the signal indicative of voltage supplied to the load, the further delayed version of the signal indicative of voltage supplied to the load being delayed less than the delayed version of the signal indicative of voltage supplied to the load, and, responsive thereto, disabling coupling of the higher voltage source supply to the higher level voltage rail.

16. The method of claim 14 , wherein the activation code is also used in deactivating the switches coupling the higher voltage source supply to the higher level voltage rail.

17. The method of claim 16 , wherein the switches are deactivated over time in a ramping manner.

18. The method of claim 17 , wherein at least some of the switches are only activated for a predetermined maximum consecutive time.