IP Library Granted Patent US 11,101,242
Granted Patent B2
US 11,101,242 · App. 16/286,282 · Granted Aug 24, 2021

Semiconductor device and method of manufacturing same

Inventor: Yuichi Sano (Tokyo, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L25/0657H01L23/562H01L25/18H01L25/50H01L2225/0651H01L2225/06506H01L2225/06562H01L2225/06586
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Quick Facts
Patent No.
US 11,101,242
App. No.
16/286,282
Granted
Aug 24, 2021
Kind
B2
Abstract

A semiconductor device includes a substrate, a first semiconductor chip on the substrate, a first adhesive material on the first semiconductor chip, a spacer chip on the first adhesive material, a second adhesive material on the spacer chip, a second semiconductor chip on the second adhesive material, and a resin material that covers the first and second semiconductor chips and the spacer chip. The spacer chip has a first region with which the resin material comes in contact is roughened and a second region that is different from the first region.

Claims (68)

1. A semiconductor device comprising:

a substrate;

a first semiconductor chip on the substrate;

a first adhesive material on the first semiconductor chip;

a spacer chip on the first adhesive material;

a second adhesive material on the spacer chip;

a second semiconductor chip on the second adhesive material; and

a resin material that covers the first and second semiconductor chips and the spacer chip, wherein

the spacer chip has a first region with which the resin material comes in contact that is roughened and a second region that is different from the first region, wherein

the first region has a larger amount of oxide than the second region.

2. The semiconductor device according to claim 1 , wherein

the first and second regions are arranged on a surface of the spacer chip above which the second semiconductor chip is arranged, and

the second semiconductor chip is arranged above the second region via the second adhesive material.

3. The semiconductor device according to claim 1 , wherein

the spacer chip has a first surface above which the second semiconductor chip is arranged via the second adhesive material and a second surface opposite to the first surface,

the first surface includes the first region, and

the second surface includes the second region.

4. The semiconductor device according to claim 1 , wherein

the second semiconductor chip is a memory chip, and

the first semiconductor chip is a controller chip configured to control the memory chip.

5. The semiconductor device according to claim 1 , wherein

an area of the first semiconductor chip on the substrate is less than an area of the spacer chip on the first adhesive layer.

6. The semiconductor device according to claim 1 , further comprising:

a metal wire connecting the substrate and the second semiconductor chip over the first region.

7. A semiconductor device comprising:

a substrate;

a first semiconductor chip on the substrate;

a first adhesive material on the first semiconductor chip;

a spacer chip on the first adhesive material;

a second adhesive material on the spacer chip;

a second semiconductor chip on the second adhesive material; and

a resin material that covers the first and second semiconductor chips and the spacer chip, wherein

the spacer chip has a first region with which the resin material comes in contact that is roughened and a second region that is different from the first region, wherein

the first region has a larger amount of carbide than the second region.

8. The semiconductor device according to claim 7 , wherein

the first and second regions are arranged on a surface of the spacer chip above which the second semiconductor chip is arranged, and

the second semiconductor chip is arranged above the second region via the second adhesive material.

9. The semiconductor device according to claim 7 , wherein

the spacer chip has a first surface above which the second semiconductor chip is arranged via the second adhesive material and a second surface opposite to the first surface,

the first surface includes the first region, and

the second surface includes the second region.

10. The semiconductor device according to claim 7 , wherein

the second semiconductor chip is a memory chip, and

the first semiconductor chip is a controller chip configured to control the memory chip.

11. The semiconductor device according to claim 7 , wherein

an area of the first semiconductor chip on the substrate is less than an area of the spacer chip on the first adhesive layer.

12. The semiconductor device according to claim 7 , further comprising:

a metal wire connecting the substrate and the second semiconductor chip over the first region.

13. A semiconductor device comprising:

a substrate;

a first semiconductor chip on the substrate;

a first adhesive material on the first semiconductor chip;

a spacer chip on the first adhesive material;

a second adhesive material on the spacer chip;

a second semiconductor chip on the second adhesive material; and

a resin material that covers the first and second semiconductor chips and the spacer chip, wherein

the spacer chip has a first region at which the resin material comes in contact,

the first region is rougher than a second region,

the spacer chip has a first surface above which the second semiconductor chip is arranged via the second adhesive material and a second surface opposite to the first surface,

the first surface includes the first region and the second region, and

the first region is made of oxide or carbide materials.

14. The semiconductor device according to claim 13 , wherein

the second semiconductor chip is a memory chip, and

the first semiconductor chip is a controller chip configured to control the memory chip.

15. The semiconductor device according to claim 13 , wherein

an area of the first semiconductor chip on the substrate is less than an area of the spacer chip on the first adhesive layer.

16. The semiconductor device according to claim 13 , further comprising:

a metal wire connecting the substrate and the second semiconductor chip over the first region.

Assignments (2)
CHANGE OF NAME AND ADDRESS Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058905/0582 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2019
From: SANO, YUICHI
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 049158/0381 →