Convolutional neural network using adaptive 3D array

1. A method of training a hybrid computational system to configure a three-dimensional (3D) multiplier array comprising a predetermined number of multipliers in a convolutional neural network, the hybrid computational system comprises a field programmable gate array, a graphical processor unit, a central processing unit, a memory interface, and a controller all connected to each other via a central interconnect, and is configured to perform the method steps comprising:

determining a set of model data with a deterministic inference model using the graphical processor unit of the hybrid computational system;

programming the field programmable gate array to perform the steps further comprising:

determining activation data dimensions comprising an activation data map width, an activation data map height, a channel depth, and a batch number:

determining dimensions of filter weights comprising Kernel width, Kernel height, Kernel depth, and filter number, wherein the Kernel depth matches the channel depth; and

configuring the 3D multiplier array to increase a rate of utilization of multipliers when performing a multiply accumulate operation, wherein configuring the 3D multiplier array comprises:

in response to determining that the activation data map width is not a multiple of a first dimension of the 3D multiplier array, configuring the first dimension of the 3D multiplier array to concurrently compute for the activation data map width and the activation data map height:

configuring a second dimension of the 3D multiplier array to concurrently compute for the channel depth, the Kernel width, and the Kernel height; and

configuring a third dimension of the 3D multiplier array to compute for the filter number.

2. The method of claim 1 , further comprising:

configuring the first dimension of the 3D multiplier array to be one of the following: one half, one fourth, and equivalent to a size of the activation data map width.

3. The method of claim 1 , further configure:

configuring the second dimension of the 3D multiplier array to be one of the following: one half, one fourth, and equivalent to a size of the channel depth.

4. The method of claim 1 , further comprising:

configuring the third dimension of the multiplier layer is one of the following: one half, one fourth, and equivalent to a size of the filter set number.

5. The method of claim 1 , further comprising:

summing a layer set within the summation of the activation data map height and

summing a batch within the summation of the layer set.

6. The method of claim 5 , further comprising concurrently summing the kernel height and the kernel width, wherein the kernel height and the kernel width are summed within one loop.

7. The method of claim 1 , further comprising concurrently summing the kernel height and the kernel width, wherein the kernel height and the kernel width are summed within one loop.

8. The method of claim 1 , further comprising:

summing the channel depth within the summation of the kernel width;

summing the activation data map width within the summation of the channel depth;

summing a filter set within the summation of the activation data map height;

summing a layer set within the summation of the filter set number; and

summing a batch within the summation of the layer set.

9. The method of claim 8 , further comprising:

concurrently summing the activation data map width and the activation data map height to yield a concurrent result, wherein the activation data map width and the activation data map height are summed within one loop; and

dividing the concurrent result by the activation data map width.

10. The method of claim 9 , further comprising concurrently summing the channel depth, the kernel width and the kernel height, wherein the channel depth, the kernel width and the kernel height are summed within one loop.

11. The method of claim 1 , wherein the memory and the interface controller are further connected to a persistent memory disk, a system memory, and a read only memory.

12. The method of claim 1 , wherein the field programmable gate array is further connected to the memory interface via an interconnect from a programmable logic circuit to memory.

13. The method of claim 1 , wherein the central interconnect is further connected to an input and output interface and a network interface.

14. The method of claim 1 , wherein the field programmable gate array, the graphical processor unit, and the central processing unit are each capable of providing a neural net.