Semiconductor memory device

1. A semiconductor memory device comprising:

a first plane including a memory cell array;

a second plane including a memory cell array;

a control circuit configured to control operations performed on the first and second planes separately and independently; and

a first register for storing a condition value related to a condition of an operation to be performed on one of the planes, wherein:

when a first command to store a first condition value in a first address of the first register is received, the control circuit specifies a plane to which the first address has been allocated;

when the first plane is specified by the first address, the control circuit determines whether the first plane is in a command receivable state;

when the control circuit determines that the first plane is in the command receivable state, the control circuit stores the first condition value in the first address of the first register;

when the first condition value is stored in the first address of the first register, and a second command for a first read operation on the first plane is received, the control circuit determines whether the first plane is in a command receivable state; and

when the control circuit determines that the first plane is in the command receivable state, the control circuit executes the first read operation based on the first condition value, and further wherein:

when the first command is received while the second plane is not in the command receivable state, the control circuit still stores the first condition value in the first address of the first register;

when the second command is received while the second plane is not in the command receivable state, the control circuit still executes the first read operation based on the first condition value;

when a third command to store a second condition value in a second address of the first register is received, the control circuit specifies a plane to which the second address has been allocated;

when the second plane is specified by the second address, the control circuit determines whether the second plane is in a command receivable state; and

when the control circuit determines that the second plane is not in the command receivable state, the control circuit does not store the second condition value in the second address of the first register.

2. The semiconductor memory device according to claim 1 , further comprising:

a second register having a first storage area and a second storage area, wherein

the condition value stored in the first address of the first register is moved to the first storage area of the second register prior to execution of an operation on the first plane that is based on the condition value, and

the condition value stored in the second address of the first register is moved to the second storage area of the second register prior to execution of an operation on the second plane that is based on the condition value.

3. The semiconductor memory device according to claim 1 , wherein the control circuit includes a first control circuit configured to control operations performed on the first plane and a second control circuit configured to control operations performed on the second plane.

4. The semiconductor memory device according to claim 3 , further comprising:

a ready/busy circuit configured to output a first ready/busy signal indicating whether or not the first plane is in a command receivable state and a second ready/busy signal indicating whether or not the second plane is in a command receivable state.

5. The semiconductor memory device according to claim 4 , wherein the ready/busy circuit is configured to generate the first ready/busy signal based on an operation state of the first control circuit and not the second control circuit and to generate the second ready/busy signal based on an operation state of the second control circuit and not the first control circuit.

6. The semiconductor memory device according to claim 5 , further comprising:

a voltage generation circuit configured to generate voltages for operations performed on the first and second planes, the voltage generation circuit including a first voltage generation circuit under control of the first control circuit to generate voltages for the first plane and a second voltage generation circuit under control of the second control circuit to generate voltages for the second plane.

7. A method of controlling an operation performed on first and second planes of a semiconductor memory device, said method comprising:

allocating first and second addresses in a register for the first and second planes, respectively;

upon receiving a first command to store a first condition value for performing an operation on one of the planes, the first command including an address of the register, determining that the first command is specifying the first plane if the address in the first command is the one that has been allocated to the first plane and that the first command is specifying the second plane if the address in the first command is the one that has been allocated to the second plane;

determining that the plane specified by the first command is in a command receivable state;

upon determining that the plane specified by the first command is in a command receivable state is in the command receivable state, storing the first condition value in the first address of the first register;

when the first condition value is stored in the first address of the first register, and a second command for a first read operation on the first plane is received, further determining whether the first plane is in a command receivable state;

upon further determining that the first plane is in the command receivable state, executing the first read operation based on the first condition value;

upon receiving a third command to store a second condition value in a second address of the first register, determining that the third command is specifying the second plane; and

determining whether the second plane is in a command receivable state,

wherein, upon determining that the second plane is not in the command receivable state, the second condition value is not stored in the second address of the first register, and

wherein, when the first command is received while the second plane is not in the command receivable state, the first condition value is still stored in the first address of the first register, and when the second command is received while the second plane is not in the command receivable state, the first read operation is still executed based on the first condition value.

8. The method according to claim 7 , further comprising:

moving the condition value stored in the first address of the first register to a first storage area of a second register prior to execution of an operation on the first plane that is based on the condition value, and

moving the condition value stored in the second address of the first register to a second storage area of the second register prior to execution of an operation on the second plane that is based on the condition value.

9. The method according to claim 7 , wherein the semiconductor memory device includes a first control circuit configured to control operations performed on the first plane and a second control circuit configured to control operations performed on the second plane.

10. The method according to claim 9 , further comprising:

outputting a first ready/busy signal indicating whether or not the first plane is in a command receivable state and a second ready/busy signal indicating whether or not the second plane is in a command receivable state.

11. The method according to claim 10 , further comprising:

generating the first ready/busy signal based on an operation state of the first control circuit and not the second control circuit; and

generating the second ready/busy signal based on an operation state of the second control circuit and not the first control circuit.

12. The method according to claim 11 , further comprising:

generate voltages for operations performed on the first plane under control of the first control circuit; and

generate voltages for operations performed on the second plane under control of the second control circuit.