Device and method for data reception

1. A receiver device, comprising:

a first differential receiver configured to output a first single ended signal based on a voltage between a first wire and a second wire of three or more wires;

first delay compensation circuitry configured to generate a first compensated single ended signal by delaying the first single ended signal;

clock recovery circuitry configured to generate a recovered clock signal at least partially based on the first compensated single ended signal; and

first latch circuitry configured to latch the first compensated single ended signal in synchronization with the recovered clock signal,

wherein a delay time of the first delay compensation circuitry used in reception of a first symbol is at least partially based on a voltage between the first wire and the second wire in reception of a second symbol transmitted before the first symbol.

2. The receiver device according to claim 1 , wherein the delay time of the first delay compensation circuitry used in the reception of the first symbol is at least partially based on whether the voltage between the first wire and the second wire in the reception of the second symbol is in a first state or a second state, and

wherein an absolute value of the voltage between the first wire and second wire in the second state is smaller than an absolute value of the voltage between the first wire and the second wire in the first state.

3. The receiver device according to claim 1 , further comprising:

a second differential receiver connected to the second wire and a third wire of the three or more wires and configured to output a second single ended signal; and

a third differential receiver connected to the third wire and the first wire and configured to output a third single ended signal, and

wherein the delay time of the first delay compensation circuitry is at least partially based on the second single ended signal and the third single ended signal.

4. The receiver device according to claim 1 , wherein signals generated in accordance with a mobile industry processor interface (MIPI) C-PHY standard are supplied to the first wire and the second wire.

5. The receiver device according to claim 1 , further comprising:

a second receiver configured to output a second single ended signal based on a voltage between the second wire and a third wire of the three or more wires;

a third receiver configured to output a third single ended signal based on a voltage between the third wire and the first wire;

second delay compensation circuitry configured to generate a second compensated single ended signal by delaying the second single ended signal; and

third delay compensation circuitry configured to generate a third compensated single ended signal delaying the third single ended signal,

wherein a delay time of the second delay compensation circuitry used in the reception of the first symbol is at least partially based on a voltage between the second wire and the third wire in the reception of the second symbol, and

wherein a delay time of the third delay compensation circuitry used in the reception of the first symbol is at least based on a voltage between the third wire and the first wire in the reception of the second symbol.

6. The receiver device according to claim 5 , further comprising:

first hold delay circuitry configured to generate a first previous symbol single ended signal by delaying the first compensated single ended signal;

second hold delay circuitry configured to generate a second previous symbol single ended signal by delaying the second compensated single ended signal; and

third hold delay circuitry configured to generate a third previous symbol single ended signal by delaying the third compensated single ended signal,

wherein the delay time of the first delay compensation circuitry is at least partially based on the second previous symbol single ended signal and the third previous symbol single ended signal.

7. The receiver device according to claim 6 , wherein the delay time of the first delay compensation circuitry is at least partially based on an exclusive OR of the second previous symbol single ended signal and the third previous symbol single ended signal.

8. The receiver device, according to claim 6 , wherein the delay time of the second delay compensation circuitry is at least partially based on the third previous symbol single ended signal and the first previous symbol single ended signal, and

wherein the delay time of the third delay compensation circuitry is at least partially based on the first previous symbol single ended signal and the second previous symbol single ended signal.

9. The receiver device according to claim 8 , wherein the delay time of the second delay compensation circuitry is at least partially based on an exclusive OR of the third previous symbol single ended signal and the first previous symbol single ended signal, and

wherein the delay time of the third delay compensation circuitry is at least partially based on an exclusive OR of the first previous symbol single ended signal and the second previous symbol single ended signal.

10. The receiver device according to claim 5 , wherein the delay time of the second delay compensation circuitry used in the reception of the first symbol is at least partially based on a voltage between the second wire and the third wire in the reception of the first symbol, and

wherein the delay time of the third delay compensation circuitry used in the reception of the first symbol is at least partially on a voltage between the third wire and the first wire in the reception of the first symbol.

11. The receiver device according to claim 10 , further comprising:

first hold delay circuitry configured to generate a first previous symbol single ended signal by delaying the first compensated single ended signal;

second hold delay circuitry configured to generate a second previous symbol single ended signal by delaying the second compensated single ended signal; and

third hold delay circuitry configured to generate a third previous symbol single ended signal by delaying the third compensated single ended signal,

wherein the delay time of the first delay compensation circuitry is at least partially based on the second single ended signal, the third single ended signal, the second previous symbol single ended signal, and the third previous symbol single ended signal.

12. The receiver device according to claim 11 , wherein the delay time of the first delay compensation circuitry is at least partially based on an exclusive OR of the second single ended signal and the third single ended signal, and an exclusive OR of the second previous symbol single ended signal and the third previous symbol single ended signal.

13. The receiver device according to claim 11 , wherein the delay time of the first delay compensation circuitry is selected from among four delay times based on the second single ended signal, the third single ended signal, the second previous symbol single ended signal, and the third previous symbol single ended signal.

14. The receiver device according to claim 11 , wherein the delay time of the second delay compensation circuitry is at least partially based on the third single ended signal, the first single ended signal, the third previous symbol single ended signal, and the first previous symbol single ended signal, and

wherein the delay time of the third delay compensation circuitry is at least partially based on the first single ended signal, the second single ended signal, the first previous symbol single ended signal, and the second previous symbol single ended signal.

15. The receiver device according to claim 1 , wherein the delay time of the first delay compensation circuitry used in the reception of the first symbol is further based on a voltage between the first wire and the second wire in the reception of the first symbol.

16. The receiver device according to claim 15 , wherein the delay time of the first delay compensation circuitry used in the reception of the first symbol is at least partially based on whether the voltage between the first wire and the second wire in the reception of the first symbol and the voltage between the first wire and the second wire in the reception of the second symbol are in a first state or a second state, and

wherein an absolute value of the voltage between the first wire and the second wire in the second state is smaller than an absolute value of the voltage between the first wire and the second wire in the first state.

17. A receiver device, comprising:

a first differential receiver configured to output a first single ended signal based on a voltage between a first wire and a second wire;

a second differential receiver configured to output a second single ended signal based on a voltage between the second wire and a third wire;

a third differential receiver configured to output a third single ended signal based on a voltage between the third wire and the first wire; and

first state identification circuitry configured to generate a first state signal indicating a state of a voltage between the first wire and the second wire based on the second single ended signal and the third single ended signal.

18. The receiver device according to claim 17 , wherein the first state identification circuitry is further configured to generate the first state signal based on one of the second single ended signal and the third single ended signal.

19. The receiver device according to claim 17 , further comprising:

second state identification circuitry configured to generate a second state signal indicating a state of a voltage between the second wire and the third wire based on the third single ended signal and the first single ended signal; and

third state identification circuitry configured to generate a third state signal indicating a state of a voltage between the third wire and the first wire based on the first single ended signal and the second single ended signal.

20. A data reception method, comprising:

outputting a first single ended signal based on a voltage between a first wire and a second wire;

generating a first compensated single ended signal by delaying the first single ended signal;

generating a recovered clock signal based on the first compensated single ended signal; and

latching the first compensated single ended signal in synchronization with the recovered clock signal,

wherein generating the first compensated single ended signal comprises controlling a delay time applied to the first single ended signal in generating the first compensated single ended signal in reception of a first symbol, based on a voltage between the first wire and the second wire in reception of a second symbol transmitted before the first symbol.