Multi-level memory hierarchy

1. A method of hierarchical structuring a multi-level memory in a convolutional neural network, comprising:

partitioning a memory into a plurality of sections;

partitioning the plurality of sections into a plurality of stripes;

utilizing input data from the plurality of stripes in each of at least two multiply accumulate (MAC) arrays;

outputting an intermediate result from the multiply accumulate (MAC) arrays to at least one of the plurality of stripes of a result buffer;

looping back the intermediate result from the at least one of the plurality of stripes of the result buffer of a shared data buffer to at least one of the plurality of stripes of an input data buffer forming a chain process, wherein the shared buffer is shared by the at least two multiply accumulate (MAC) arrays;

outputting a final result from the at least one of the plurality of stripes of the result buffer to at least one of the plurality of stripes of an output buffer;

partitioning a multiply accumulate (MAC) weight buffer section;

partitioning an input data buffer section;

partitioning a result buffer section;

partitioning an output buffer section;

partitioning a shared data buffer section;

partitioning a bit test weight memory section;

partitioning a bit test data memory section;

partitioning an external random access memory section;

partitioning the input data buffer section into a plurality of input buffer data stripes;

partitioning the result buffer section into a plurality of result buffer stripes;

partitioning the output buffer section into a plurality of output buffer stripes;

partitioning the shared data buffer section into a plurality of shared data stripes;

partitioning the bit test data memory section into a plurality of bit test data memory stripes;

receiving the bit test weights and the input data from the external random access memory section;

decompressing the received bit test weights from the bit test weight memory section; and

storing the decompressed bit test weights from the bit test weight memory section in the multiply accumulate (MAC) weight buffer section;

importing input data from the bit test data memory section to at least one of the plurality of stripes of the shared data buffer section;

importing the input data from the at least one of the plurality of stripes of the shared data buffer section to the at least one of the plurality of stripes of the input data buffer section; and

receiving weights from the multiply accumulate (MAC) weight buffer section and the input data buffer section at the multiply accumulate (MAC) arrays.

2. The method of hierarchical structuring the multi-level memory of claim 1 , further comprising:

outputting the final result from the at least one of the plurality of stripes of the output buffer section to the at least one of the plurality of stripes of the shared data buffer section;

outputting the final result from the at least one of the plurality of stripes of the shared data buffer section to the at least one of the plurality of stripes of the bit test data memory section; and

outputting the final result from the at least one of the plurality of stripes of the bit test data memory section to the external random access memory section.

3. The method of hierarchical structuring the multi-level memory of claim 2 , further comprising:

outputting the final result from the at least one of the plurality of stripes of the output buffer section to the at least one of the plurality of stripes of the shared data buffer section;

outputting the final result from the at least one of the plurality of stripes of the shared data buffer section to the at least one of the plurality of stripes of the bit test data memory section; and

outputting the final result from the at least one of the plurality of stripes of the bit test data memory section to the external random access memory section.

4. The method of hierarchical structuring the multi-level memory of claim 3 , further comprising:

storing a width component of a data set so that a width component increases linearly in a first address direction in a memory array;

storing a height component of the data set so that a height component increases linearly in a second address direction orthogonal to the first address direction in the memory array; and

storing a depth component of the data set so that a depth component increases linearly in a third address direction symmetric to the first address direction and the second address direction in the memory array.

5. The method of hierarchical structuring the multi-level memory of claim 3 , further comprising:

storing a width component of a data set so that a width component increases linearly in a first address direction in a memory array;

storing a height component of the data set so that a height component increases linearly in a second address direction orthogonal to the first address direction in the memory array; and

storing a depth component of the data set so that a depth component increases linearly in a third address direction symmetric to the first address direction and the second address direction in the memory array.

6. A method of hierarchical structuring a multi-level memory in a convolutional neural network, comprising:

partitioning a memory into a plurality of sections;

partitioning the plurality of sections into a plurality of stripes;

utilizing input data from the plurality of stripes in each of at least two multiply accumulate (MAC) arrays;

outputting an intermediate result from the multiply accumulate (MAC) arrays to at least one of the plurality of stripes of a result buffer;

looping back the intermediate result from the at least one of the plurality of stripes of the result buffer of a shared data buffer to at least one of the plurality of stripes of an input data buffer forming a chain process, wherein the shared buffer is shared by the at least two multiply accumulate (MAC) arrays;

outputting a final result from the at least one of the plurality of stripes of the result buffer to at least one of the plurality of stripes of an output buffer;

partitioning a multiply accumulate (MAC) weight buffer section;

partitioning an input data buffer section;

partitioning a result buffer section;

partitioning an output buffer section;

partitioning a shared data buffer section;

partitioning a bit test weight memory section;

partitioning a bit test data memory section;

partitioning an external random access memory section;

partitioning the input data buffer section into a plurality of input buffer data stripes;

partitioning the result buffer section into a plurality of result buffer stripes;

partitioning the output buffer section into a plurality of output buffer stripes;

partitioning the shared data buffer section into a plurality of shared data stripes;

partitioning the bit test data memory section into a plurality of bit test data memory stripes;

partitioning the plurality of input buffer data stripes into a plurality of input buffer data tiles;

partitioning the plurality of result buffer stripes into a plurality of result buffer tiles;

partitioning the plurality of output buffer stripes into a plurality of output buffer tiles;

partitioning the plurality of shared data stripes into a plurality of shared data tiles;

partitioning the plurality of bit test data stripes into a plurality of bit test data memory tiles;

importing input data from the bit test data memory section to at least one of the plurality of tiles of the shared data buffer section;

importing the input data from the at least one of the plurality of tiles of the shared data buffer section to the at least one of the plurality of tiles of the input data buffer section; and

receiving weights from the multiply accumulate (MAC) weight buffer section and the input data buffer section at the multiply accumulate (MAC) arrays.

7. The method of hierarchical structuring the multi-level memory of claim 6 , further comprising:

outputting the final result from the at least one of the plurality of tiles of the output buffer section to the at least one of the plurality of tiles of the shared data buffer section;

outputting the final result from the at least one of the plurality of tiles of the shared data buffer section to the at least one of the plurality of tiles of the bit test data memory section; and

outputting, the final result from the at least one of the plurality of tiles of the bit test data memory section to the external random access memory section.

8. The method of hierarchical structuring the multi-level memory of claim 7 , further comprising;

storing a width component a data set so that a width component increases linearly in a first address direction in a memory array;

storing a height component of the data set so that a height component increases linearly in a second address direction orthogonal to the first address direction in the memory array; and

storing a depth component of the data set so that a depth component increases linearly in a third address direction symmetric to the first address direction and the second address direction in the memory array.

9. The method of hierarchical structuring the multi-level memory of claim 7 , further comprising:

storing a width component of a data set so that a width component increases linearly in a first address direction in a memory array;

storing a height component of the data set so that a height component increases linearly in a second address direction orthogonal to the first address direction in the memory array; and

storing a depth component of the data set so that a depth component increases linearly in a third address direction symmetric to the first address direction and the second address direction in the memory array.