IP Library Granted Patent US 10,665,614
Granted Patent B2
US 10,665,614 · App. 16/289,662 · Granted May 26, 2020

Display panel and method for manufacturing thin film transistor substrate

Inventor: Hiroshi Hayashi (Tokyo, JP)
Assignee: JOLED INC.
H01L27/1225G09F9/30G09F9/33H01L21/8234H01L27/08H01L27/088H01L27/124H01L27/127H01L27/1222H01L27/1229H01L27/1251H01L29/42384H01L29/4908H01L29/78645H01L29/78696H01L51/50H01L27/3262
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Quick Facts
Patent No.
US 10,665,614
App. No.
16/289,662
Granted
May 26, 2020
Kind
B2
Abstract

A display panel includes a substrate, a display element, a plurality of pixels arranged in a matrix, a drive circuit that drives the display element, a switching transistor in each of the plurality of pixels and selectively performs switching on the pixel that is to be caused to emit light, a first drive transistor in each of the plurality of pixels and drives a light-emitting element in the pixel, and a second drive transistor in the drive circuit. The switching transistor that is in each of the plurality of pixels, the first drive transistor that is in each of the plurality of pixels, and the second drive transistor in the drive circuit include oxide semiconductors. The switching transistor in each of the plurality of pixels and the second drive transistor in the drive circuit have a higher mobility than the first drive transistor in each of the plurality of pixels.

Claims (28)

1. A display panel comprising:

a substrate;

a display element disposed on the substrate;

a plurality of pixels arranged in a matrix in the display element;

a drive circuit that is disposed on the substrate and drives the display element;

a switching transistor that is disposed in each of the plurality of pixels and selectively performs switching on the pixel that is to be caused to emit light;

a first drive transistor that is disposed in each of the plurality of pixels and drives a light-emitting element in the pixel; and

a second drive transistor in the drive circuit,

wherein

the switching transistor that is disposed in each of the plurality of pixels includes a first gate electrode and a first oxide semiconductor layer that is used as a first channel, the first drive transistor that is disposed in each of the plurality of pixels includes a second gate electrode and a second oxide semiconductor layer that is used as a second channel, and the second drive transistor in the drive circuit includes a third gate electrode and a third oxide semiconductor layer that is used as a third channel,

the first oxide semiconductor layer comprises a first oxide semiconductor material, the second oxide semiconductor layer comprises a second oxide semiconductor material and the third oxide semiconductor layer comprises a third oxide semiconductor material, and

the first oxide semiconductor material and the third oxide semiconductor material have a higher mobility than the second oxide semiconductor material.

2. The display panel according to claim 1 ,

wherein the first oxide semiconductor material, the second oxide semiconductor material and the third oxide semiconductor material are different from each other in element structure.

3. The display panel according to claim 1 ,

wherein the first oxide semiconductor material, the second oxide semiconductor material and the third oxide semiconductor material are the same in element structure and different in element ratio.

4. The display panel according to claim 1 , wherein the first oxide semiconductor layer has a substantially uniform thickness.

5. The display panel according to claim 1 , wherein the second oxide semiconductor layer has a substantially uniform thickness.

6. The display panel according to claim 1 , further comprising a channel protection layer over the first oxide semiconductor layer and over the second oxide semiconductor layer.

7. The display panel according to claim 6 , wherein the channel protection layer is a continuous layer over both the first oxide semiconductor layer and the second oxide semiconductor layer.

8. The display panel according to claim 6 , wherein the channel protection layer directly contacts at least one of the first oxide semiconductor layer or the second oxide semiconductor layer.

9. The display panel according to claim 6 , further comprising:

a source electrode extending through the channel protection layer to electrically connect to the first oxide semiconductor layer; and

a drain electrode extending through the channel protection layer to electrically connect to the first oxide semiconductor layer.

10. The display panel according to claim 6 , further comprising:

a source electrode extending through the channel protection layer to electrically connect to the second oxide semiconductor layer; and

a drain electrode extending through the channel protection layer to electrically connect to the second oxide semiconductor layer.

11. The display panel according to claim 1 , wherein a top-most surface of the first oxide semiconductor layer is substantially planar across an entirety of the first oxide semiconductor layer.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2019
From: HAYASHI, HIROSHI
To: JOLED INC.
Reel/Frame 048473/0563 →