Memory system and method of controlling memory system for calculating voltage value for reading data
View Patent ↗A memory system includes a first memory, a second memory, and a first circuit. The first memory includes a memory cell array including memory cell transistors, and a peripheral circuit configured to read data of a plurality of bits stored in a memory cell transistor of the memory cell array based on a comparison between threshold voltages of the memory cell transistor and at least a part of n determination voltages (n≥3). The first circuit is configured to calculate an estimated value of each of n−m determination voltages based on values of m determination voltages (2≤m≤n−1) among the n determination voltages, and calculate a difference between a value of each of the n−m determination voltages and a corresponding estimated value. The second memory is configured to store values of the m determination voltages and the difference for each of the n−m determination voltages.
1. A memory system comprising:
a first memory including a memory cell array including memory cell transistors, and a peripheral circuit configured to read data of a plurality of bits stored in a memory cell transistor of the memory cell array based on a comparison between threshold voltages of the memory cell transistor and at least a part of n determination voltages (n≥3);
a first circuit configured to calculate an estimated value of each of n−m determination voltages based on values of m determination voltages (2≤m≤n−1) among the n determination voltages, and calculate a difference between a value of each of the n−m determination voltages and a corresponding estimated value;
a second memory configured to store values of the m determination voltages and the difference for each of the n−m determination voltages; and
a second circuit configured to calculate an estimated value of each of n−m determination voltages based on the values of the m determination voltages read from the second memory, and calculate a value of each of n−m determination voltages based on a corresponding estimated value calculated thereby and a corresponding difference read from the second memory, respectively.
2. The memory system according to claim 1 , further comprising a memory controller configured to:
carry out error correction processing with respect to data read from the memory cell transistor, and
cause the first circuit to perform calculation of the estimated value of each of the n−m determination voltages and the difference for each of the n−m determination voltage, based on a result of the error correction processing.
3. The memory system according to claim 2 , wherein the memory controller is further configured to:
update values of the n determination voltages by shifting a value of at least part of the n determination voltages, when the error correction processing is unsuccessful, and
cause the first circuit to perform calculation of the estimated value of each of the n−m determination voltages and the difference for each of the n−m determination voltage, using updated values of the n determination voltages.
4. The memory system according to claim 2 , wherein the first circuit is integrated with the memory controller.
5. The memory system according to claim 2 , wherein the first circuit is externally provided from the first memory, the second memory, and the memory controller.
6. The memory system according to claim 1 , wherein the first circuit is integrated with the first memory.
7. The memory system according to claim 1 , further comprising:
a memory controller configured to control the peripheral circuit to read the data of the plurality of bits stored in the memory cell transistor of the memory cell array, using the value of each of the n−m determination voltages calculated by the second circuit and the values of the m determination voltages read from the second memory.
8. The memory system according to claim 7 , wherein any one of the first circuit and the second circuit is integrated with the memory controller.
9. The memory system according to claim 7 , wherein any one of the first circuit and the second circuit is externally provided from the first memory, the second memory, and the memory controller.
10. The memory system according to claim 1 , wherein any one of the first circuit and the second circuit is integrated with the first memory.
11. The memory system according to claim 1 , wherein the first circuit is configured to calculate the estimated value of each of n−m determination voltages based on interpolation of the values of the m determination voltages.
12. The memory system according to claim 1 , wherein the first circuit is configured to calculate the estimated value of each of n−m determination voltages based on extrapolation of the values of the m determination voltages.
13. A method of controlling a memory system comprising a first memory including a memory cell array including memory cell transistors, the method comprising:
determining values of n determination voltages (n≥3) to be used to read data of a plurality of bits stored in a memory cell transistor based on a comparison between threshold voltages of the memory cell transistor and at least a part of the n determination voltages;
calculating an estimated value of each of n−m determination voltages based on the values of m determination voltages (2≤m≤n−1) among the n determination voltages;
calculating a difference between a value of each of the n−m determination voltages and a corresponding estimated value;
storing, in memory, the values of the m determination voltages and the difference for each of the n−m determination voltages, without storing the determined values of the n−m determination voltages;
calculating an estimated value of each of n−m determination voltages based on the values of the m determination voltages stored in the memory; and
calculating a value of each of n−m determination voltages based on a corresponding estimated value calculated thereby and a corresponding difference stored in the memory, respectively.
14. The method of claim 13 , further comprising:
carrying out error correction processing with respect to data read from the memory cell transistor, wherein
when the error correction processing is unsuccessful, the calculating the estimated value of each of the n−m determination voltages is carried out.
15. The method of claim 13 , further comprising:
updating values of the n determination voltages by shifting a value of at least part of the n determination voltages, when the error correction processing is unsuccessful, wherein
the calculating the estimated value of each of the n−m determination voltages is carried out, using updated values of the n determination voltages.
16. The method of claim 13 , further comprising:
reading data of the plurality of bits from the memory cell transistor, using the values of the m determination voltages stored in the second memory and the value of each of the n-m determination voltages calculated from the values of the m determination voltages stored in the second memory.
17. The method of claim 13 , wherein the estimated value of each of n−m determination voltages is calculated based on interpolation of the values of the m determination voltages.
18. The method of claim 13 , wherein the estimated value of each of n−m determination voltages is calculated based on extrapolation of the values of the m determination voltages.