Memory system
According to one embodiment, a controller is configured to write four-bit data in each of memory cells, and read first data item from the memory cells through application of a first voltage to a word line. The controller is configured to read second data items by repeating a first operation of reading data including data of respective first bits of the memory cells through application of two voltages to the word line at different timings while changing the two voltages in each first operation from the two voltages in another first operation. The controller is configured to mask part of each of the second data items using the first data.
1. A memory system comprising:
a semiconductor memory including memory cells and a word line coupled to the memory cells; and
a controller configured to:
write four-bit data in each of the memory cells,
read first data item from the memory cells through application of a first voltage to the word line,
read a plurality of second data items by repeating a first operation of reading data including data of respective first bits of the memory cells through application of two voltages to the word line at different timings while changing the two voltages in each first operation from the two voltages in another first operation, and
mask part of each of the second data items using the first data item.
2. The system of claim 1 , wherein:
the first voltage has a magnitude between one of the two voltages and the other of the two voltages.
3. The system of claim 1 , wherein:
the first data item is obtained by determining in which one of two states each of the memory cells is, based on the first voltage, and
one of the second data items is obtained by determining in which one of sixteen states each of the memory cells is.
4. The system of claim 3 , wherein the first data item includes a plurality of first bits,
each of the first bits is based on in which one of two states one of the memory cells is, based on the first voltage,
each of the memory cells stores data in a first digit bit, a second digit bit, a third digit bit, and a fourth digit bit,
each of the second data items includes a plurality of second bits, and
each of the second bits of one of the second data items includes a data stored in the first digit bit of one of the memory cells.
5. The system of claim 1 , wherein:
the controller is configured to mask one of the second data items by performing a logical operation on the one of the second data items and the first data item.
6. The system of claim 1 , wherein:
the controller is configured to change one of the two voltages within a first range and change the other of the two voltages within a second range every time the first operation is repeated.
7. The system of claim 6 , wherein:
the controller is further configured to:
obtain a plurality of third data items through the masking with the first data item,
determine a plurality of first counts of memory cells estimated to have threshold voltages respectively corresponding to a plurality of voltages within the first range based on the third data items, and
detect, from the first counts, one or two or more second counts that are local minimum within the first range.
8. The system of claim 7 , wherein:
the controller is further configured to:
select, when the two or more second counts are detected, a third count from the two or more second counts that are nearest to a number of the memory cells×Y/16 (where Y is a natural number not larger than 16), and
use a voltage corresponding to the third count to determine whether a threshold voltage of one of the memory cells is higher than a Y th lowest boundary voltage of fifteen boundary voltages.
9. The system of claim 8 , wherein:
the controller is further configured to select the first range based on the word line.
10. The system of claim 9 , wherein:
the controller is further configured to select the first voltage based on the first range.
11. A memory system comprising:
a semiconductor memory including memory cells and a word line coupled to the memory cells; and
a controller configured to:
write p-bit (where p is a natural number not lower smaller than 2) data in each of the memory cells,
read a plurality of first data items by repeating a first operation of reading data including data in the memory cells through application of a first voltage to the word line at different timings while changing the first voltage in each first operation from the first voltage in another first operation,
determine a plurality of first counts of memory cells estimated to have threshold voltages respectively corresponding to a plurality of voltages within a first range based on the first data items,
detect, from the first counts, one or two or more second counts that are local minimum within the first range,
select, when the two or more second counts are detected, a third count from the two or more second counts that are nearest to a number of the memory cells×Y/2 p (where Y is a natural number not more than 2 p ), and
use a voltage corresponding to the third count to determine whether a threshold voltage of one of the memory cells is higher than a Y th lowest boundary voltage of 2 p −1 boundary voltages.
12. The system of claim 11 , wherein:
the controller is configured to change the first voltage within the first range every time the first operation is repeated.
13. The system of claim 11 , wherein:
each of the first data items includes a plurality of first bits, and
each of the first bits is based on in which one of two states one of the memory cells is, based on the first voltage.