Semiconductor storage device

1. A semiconductor storage device, comprising:

a plurality of memory cells; and

a first circuit configured to:

read data from a subset of the memory cells,

determine whether the data as read from the subset contains an error,

calculate a bit error rate for the subset if the subset contains an error, and

perform a recovery processing on the subset if the calculated bit error rate is less than a first threshold value, wherein

the first circuit is configured to not perform the recovery processing on the subset when the calculated bit error rate is less than or equal to the second threshold value but greater than a second threshold value.

2. The semiconductor storage device according to claim 1 , wherein the first circuit calculates the bit error rate by repeatedly writing data to the subset and reading the data from the subset.

3. The semiconductor storage device according to claim 1 , wherein the first circuit is further configured to not perform the recovery processing on the subset when the calculated bit error rate is greater than the first threshold value.

4. The semiconductor storage device according to claim 1 , wherein the first circuit comprises a comparator storing the first threshold value and the second threshold value.

5. The semiconductor storage device according to claim 1 , wherein the first circuit comprises an error correction coding circuit configured to determine whether the data as read from the subset contains an error.

6. The semiconductor storage device according to claim 5 , wherein the error correction coding circuit is configured to generate a bit mask signal by which only particular memory cells having detected errors in the subset are subjected to recovery processing.

7. The semiconductor storage device according to claim 1 , wherein only particular memory cells having detected errors in the subset are subjected to recovery processing.

8. The semiconductor storage device according to claim 1 , wherein the recovery processing comprises repeatedly writing random data to the subset.

9. The semiconductor storage device according to claim 8 , wherein the number of repeated writings of random data to the subset in the recovering processing is limited to a predetermined limit.

10. The semiconductor storage device according to claim 1 , wherein the subset is a page unit of the plurality of memory cells.

11. The semiconductor storage device according to claim 1 , wherein the plurality of memory cells are magnetoresistive random access memory cells.

12. The semiconductor storage device according to claim 1 , wherein the first circuit is configured to perform the recovery processing during an idle state of the semiconductor storage device.

13. A semiconductor memory device, comprising:

a plurality of memory cells;

a peripheral circuit including an error correction coding circuit and a comparator and configured to:

read data from a subset of the memory cells,

detect whether the data as read from the subset contains an error by an output of the error correction coding circuit,

calculate a bit error rate for the subset when the subset contains an error by repeatedly writing and reading data to and from the subset and detecting a total number fail bits in the subset after each writing,

determine a hard breakdown failure has occurred when the comparator indicates the calculated bit error rate is greater than or equal to a first threshold value stored in the comparator, and

perform a recovery processing on the subset when the comparator indicates the calculated bit error rate is less than the first threshold value but greater than a second threshold value stored in the comparator, the recovery processing comprising repeatedly writing random data to the subset up to a predetermined limit of repeated writings.

14. The semiconductor memory device according to claim 13 , wherein the peripheral circuit is configured to calculate the bit error rate and perform the recovery processing during an idle state of the semiconductor memory device.

15. The semiconductor memory device according to claim 13 , wherein the error correction coding circuit is configured to generate a bit mask signal by which only particular memory cells having detected errors in the subset are subjected to recovery processing.

16. The semiconductor memory device according to claim 13 , wherein the subset is a page unit of the plurality of memory cells.

17. A method of operating a semiconductor storage device having a plurality of memory cells, the method comprising:

reading data from a subset of the plurality of memory cells;

detecting whether the data as read from the subset contains an error by an output of an error correction coding circuit;

calculating a bit error rate for the subset when the subset contains an error by repeatedly writing and reading data to and from the subset and detecting a total number fail bits in the subset after each writing;

determining a hard breakdown failure has occurred when the calculated bit error rate is greater than or equal to a first threshold value; and

performing a recovery processing on the subset when the calculated bit error rate is less than the first threshold value but greater than a second threshold value, the recovery processing comprising repeatedly writing random data to the subset up to a predetermined limit of repeated writings.

18. The method according to claim 17 , wherein the calculating of the bit error rate and the performing the recovery processing are controlled to occur during an idle state of the semiconductor storage device.

19. The method according to claim 17 , further comprising:

generating a bit mask signal by which only particular memory cells having detected errors in the subset are subjected to recovery processing.